ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
To configure the SPI interface to the above specifications perform the following steps:
1) Configure the SPI0_SSCTL register. SPI0_SSCTL.SSACTPOL=1 for active high slave select,
SPI0_SSCTL.SS_LTRIG=1 for level sensitive trigger.
2) Configure the SPI0_CTL register. Set SPI0_CTL.SLAVE=1 for slave mode, set
SPI0_CTL.CLKPOL=1 for SCLK polarity idle high, set SPI0_CTL.TXNEG=1 so that data changes
on falling edge of SCLK, set SPI0_CTL.RXNEG=0 so that data is latched into device on positive
edge of SCLK, set SPI0_CTL.DWIDTH=4 and SPI0_CTL.TX_NUM=0 for a single byte transfer and
finally set SPI0_CTL.LSB=1 for LSB first transfer.
3) If SPI slave is to transmit one byte of data to the off-chip master device, write first byte to TX
register. If no data to be transmitted write a dummy byte.
4) Enable the SPIEN bit to wait for the slave select trigger input and serial clock input from the off-chip
master device to start the data transfer at the SPI interface.
5) Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI0_CTL.UNITIEN bit
is set) or by polling the UNITIF bit which will be cleared to 0 by hardware automatically at end of
transmission.
6) Read out the received data from RX register.
7) Go to 3) to continue another data transfer or disable the GO_BUSY bit to stop data transfer.
