ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
I91200
SPI1 Controller
Slave
SCLK
MISO
MOSI
SSB
SCLK
MISO
MOSI
SS
Master
Figure 5-54 SPI1 Slave Mode Application Block Diagram
5.10.4.3
Slave Select
In master mode, the SPI controller can address up to one off-chip slave devices through the slave
select output pins SPI1_SSB. Only one slave can be addressed at any one time. If more slave address
lines are required, GPIO pins can be manually configured to provide additional SSB lines. In slave
mode, the off-chip master device drives the slave select signal SPI_SSB to address the SPI1 controller.
The slave select signal can be programmed to be active low or active high via the SPI1_SSCTL.SSLVL
bit. In addition the SPI1_SSCTL.SSLTRIG bit defines whether the slave select signals are level
triggered or edge triggered. The selection of trigger condition depends on what type of peripheral
slave/master device is connected.
5.10.4.4
Automatic Slave Select
In master mode, if the bit SPI1_SSCTL.AUTOSS is set, the slave select signals will be generated
automatically and output to SPI1_SSB pins according to registers SPI1_SSCTL.SS. In this mode, SPI
controller will assert SSB when transaction is triggered and de-assert when data transfer is finished. If
the SPI1_SSCTL.AUTOSS bit is cleared, the slave select output signals are asserted and de-asserted
by manual setting and clearing the related bits in the SPI1_SSCTL.SS register. The active level of the
slave select output signals is specified by the SPI1_SSCTL.SSLVL bit.
5.10.4.5
Serial Clock
In master mode, writing a divisor into the SPI1_CLKDIV register will program the output frequency of
serial clock to the SPI1_SCLK output port. In slave mode, the off-chip master device drives the serial
clock through the SPI1_SCLK.
5.10.4.6
Clock Polarity
The SPI1_CTL.CLKP bit defines the serial clock idle state in master mode. If CLKP = 1, the output
SPI1_SCLK is high in idle state. If CLKP=0, it is low in idle state.
5.10.4.7
Transmit/Receive Bit Length
The bit length of a transfer word is defined in SPI1_CTL.TXBITLEN bit field. It is set to define the length
of a transfer word and can be up to 32 bits in length. TXBITLEN=0x0 enables 32bit word length.
5.10.4.8
Burst Mode
The SPI controller has a burst mode controlled by the SPI1_CTL.TXNUM field. If set to 0x01, SPI
controller will burst two transactions from the SPI1_TX0 and SPI1_TX1 registers as shown in the
waveform below:
