ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 359 -
Revision 2.4
UART, SPI or I2C to fetch new application code. The memory area from which the I91200 boots is
controlled by the CBS bit in Config0 register.
6.6
Data Flash (DATAF)
The I91200 provides a data flash partition for user to store non-volatile data such as audio recordings. It
accessed through ISP procedures via the Flash Memory Controller (FMC). The size of each erasable
page is 512 byte and minimum write size is one word (4Bytes).An erase operation resets all memory in
page to value 0xFF. A write operation can only change a ‘1’ bit to a ‘0’ bit. If a subset of the page needs
to be changed, the entire 512B page must be copied to another page or into SRAM in advance as
entire page must be erased before modification. Data flash and application program memory share the
same memory space. If DFENB bit in Config0 is enabled (‘0’), the data flash base address is defined by
DFBA and application program memory size is (X-N)KB and data flash size is N KB, where X is the
total device memory size (128/64) and N is number of Kbytes reserved for data flash.
Application
Program Memory
APROM
(X-N Kbytes)
Data Flash
DATAF
(N Kbytes)
0x0000_0000
0x0001_FFFF
DFBADR[31:0]=N*1024
X=128
Application
Program Memory
APROM
(X Kbytes)
DFENB=1
DFENB=0
Figure 6-3 Flash Memory Structure
