ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 347 -
Revision 2.4
PDMA Global Control Register (PDMA_GCTL)
Register
Offset
R/W
Description
Reset Value
PDMA_GCTL
PDMA0x00
R/W
PDMA Global Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
CH3CKEN
CH2CKEN
CH1CKEN
CH0CKEN
7
6
5
4
3
2
1
0
Reserved
SWRST
Table 5-150 PDMA
Global Control Register
(PDMA_GCTL, address 0x5000_8F00)
Bits
Description
[31:12]
Reserved
Reserved.
[11]
CH3CKEN
PDMA Controller Channel 3 Clock Enable Control
1: Enable Channel 3 clock.
0: Disable Channel 3 clock.
[10]
CH2CKEN
PDMA Controller Channel 2 Clock Enable Control
1: Enable Channel 2 clock.
0: Disable Channel 2 clock.
[9]
CH1CKEN
PDMA Controller Channel 1 Clock Enable Control
1: Enable Channel 1 clock.
0: Disable Channel 1 clock.
[8]
CH0CKEN
PDMA Controller Channel 0 Clock Enable Control
1: Enable Channel 0 clock.
0: Disable Channel 0 clock.
[7:1]
Reserved
Reserved.
[0]
SWRST
PDMA Software Reset
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the internal state machine and pointers. The
contents of control register will not be cleared. This bit will auto clear after several
clock cycles.
Note: This bit can reset all channels (global reset).
