ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 430 -
Revision 2.4
7.6
Capacitive Sensing Scan (CSCAN) and Operational Amplifiers
7.6.1
Overview and Features
Capacitive Sensing Scanner has the ability to set up a capacitive sensing on up to 16 GPIO pins. The
block can do a single measurement or be set up to scan a defined set of GPIO before interrupting the
CPU. The measurement can be done rapidly against a high precision clock (HIRC) in active mode or can
be done slowly against a low frequency clock which can be done at low current in STOP or SPD power
modes. The analog portion of the circuit consists of a relaxation oscillator producing a triangle wave on
the parasitic capacitance attached to the GPIO.
7.6.2
Features
Support single mode or scan mode for pin cap sensing, maximum 16 pins supported.
Low power consumption (<10uA) touch wake up from STOP or SPD mode.
Current source generation for AGPIO (Analog enabled GPIO)
16 kinds of dummy delay time (maximum 3840 clocks setting in DUR_CNT) for additional duration of
periodical wakeup.
7.6.3
Operation
To operate the CSCAN with scan mode for multi pin capacitive sensing, the below steps is the sequence.
•
Set CTRL.PD=0 to power up CSCAN engien
•
Select the cscan timebase clock by setting SLOW_CLK
•
Set AGPIO.AGPIO for expected GPIO pin to analog mode.
•
Set CYCCNT.MASK for all the pins which will have capacitive sensing.
•
Set CYCCNT.CYCLE_CNT for numbers of cycle to time a capacitive sensing.
•
Select scan mode by setting CTRL.MODE0=1
•
Set CTRL.MODE1 for interrupt with DUR_CNT delay or not. MODE1=0 for no delay, interrupt happens
after finish all selected pins sensing. MODE1=1 for delay with DUR_CNT setting time.
•
Set CTRL.CURRENT for controlling the bias current of relaxation comparators.
•
Set CTRL.INT_EN to enable the IP interrupt
•
Enable NVIC CSCAN interrupt
•
Start the capacitive sensing with setting CTRL.EN
After interrupt happens, user program needs to read back the counter value of each pin capacitive
sensing which sotred in SBRAM for touch algorithm judgement then trigger next loop of scan. The
address is fixed for each pin, no matter pin is used for capacitive sensing or not.
SBRAM_BASE
(= 0x400F0000)
PB0
PB1
PB2
~
PB13 PB14 PB15
Offset
(unit: byte)
0x0
0x2
0x4
~
0x1A
0x1C
0x1E
7.6.4
Operational Amplifier
The ISD91200 contains two fully integrated Operational Amplifiers. These OPAs can be used for signal
amplification according to specific user requirements. These blocks are controlled by registers in the
analog block address space. This section describes these functions and registers
The internal Operational Amplifiers are fully under the control of internal registers, OPA0C0, OPA0C1,
OPA1C0, OPA1C1 and OPA1C2. These registers control enable/disable function, input path selection
and gain control.
The following diagram and table illustrate the OPA0 switch control setting and the corresponding
connections.
