MPC563XM Reference Manual, Rev. 1
938
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Conclusion: in this system configuration PWM can run with a minimum high time or low time of
2075 ns.
Note that in double match eTPU system the PWM can be serviced once in each period, and there is
no latency for minimum high time. The latency in eTPU PWM function will represent the minimum
PWM period.
Finding the WCL for PPWA on Channel 1
The following shows how to find the WCL for PPWA on channel 1.
1. Find the worst-case service time for each active channel. See step 1 of previous example.
2. Assume channel 1 has just been serviced and that channels 0 and 2 are continuously requesting
service. Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for
each time slot. See
Figure 23-73. Next Servicing for Channel 1
Channel 0 will be serviced twice and channel 2 once before channel 1 is serviced again.
3. Add time for the six-clock CPU time-slot transitions. See
.
131 clocks * 25 ns/clock = 3275 ns
Conclusion: in this system configuration PPWA can measure a period or pulse of minimum 3275
ns.
Note that PPWA function optimized for eTPU hardware can use double transition mode to measure
very narrow pulses with one service after the second transition, and latency will affect only the
minimum gap between two input pulses. Also the function threads would have more efficient
coding.
Table 23-104. Worst Case Latency for Channel 1
Two Channel 0 worst-case service times
50 clocks
Channel 1 worst-case service time
46 clocks
Channel 2 worst-case service time
11 clocks
Four 6-clock time-slot transitions
24 clocks
Total clocks
131 clocks
TPU CH1 WCL TIM
TPU CH1 WCL TIM
CHANNEL
SERVICED
WORST CASE LATENCY
CHANNEL 1
H
M
H
L
H
M
H
H
CHANNEL 0
SERVICED
CHANNEL 2
SERVICED
= 10-CYCLE TIME SLOT TRANSITION
= 4-CYCLE NOP INSTRUCTION
CHANNEL 0
SERVICED
CHANNEL 1
SERVICED