R01UH0823EJ0100 Rev.1.00
Page 1283 of 1823
Jul 31, 2019
RX23W Group
36. CAN Module (RSCAN)
36.9.1
Clock Setting
Set the CAN clock source (fCAN) as a clock source of the CAN module. Select PCLK or CANMCLK with the
GCFGL.DCS bit.
36.9.2
Bit Timing Setting
In the CAN protocol, one bit of a communication frame consists of three segments, SS, TSEG1, and TSEG2. Two of the
segments, TSEG1 and TSEG2, can be set by the CFGH register for each channel. Sample point timing can be determined
by setting two segments. This timing can be adjusted in units of 1 Time Quantum (referred to as Tq hereinafter). 1 Tq
equals to one CAN Tq clock cycle. The CAN Tq clock is obtained by selecting the clock source with the GCFGL.DCS
bit and selecting the clock division ratio with the CFGL.BRP[9:0] bits.
shows the bit timing chart.
shows an example of bit timing setting.
Figure 36.17
Bit Timing Chart
Table 36.12
Example of Bit Timing Setting
1 Bit
Set Value (Tq)
Sample Point (%)
Note: See Figure 36.17
SS
TSEG1
TSEG2
SJW
8 Tq
1
4
3
1
62.50
1
5
2
1
75.00
10 Tq
1
6
3
1
70.00
1
7
2
1
80.00
16 Tq
1
10
5
1
68.75
1
11
4
1
75.00
20 Tq
1
13
6
1
70.00
1
15
4
3
80.00
24 Tq
1
15
8
1
66.67
1
16
7
1
70.83
SS
TSEG1
TSEG2
Sample point (80%)
Sample point
80%
SJW
SJW
• SS (synchronization segment):
The SS is a segment that performs synchronization by monitoring the edge from recessive to dominant bits in the
Interframe Space.
Interframe Space consists of Intermission, Suspend Transmission, and Bus Idle. All nodes can start transmission during
Bus Idle.
• TSEG1 (time segment 1):
TSEG1 is a segment that absorbs physical delay on the CAN network. The physical delay on the CAN network is twice
of the total of the delay on the CAN bus, the delay in the input comparator, and the delay in the output driver.
• TSEG2 (time segment 2):
TSEG2 is a segment that compensates phase error due to an error in frequency .
• SJW (resynchronization jump width)
The SJW is a length to extend or reduce time segment to compensate an error in phase due to phase error .
SS = 1 Tq fixed
Set TSEG1 to a range of 4 Tq to 16 Tq.
Set TSEG2 to a range of 2 Tq to 8 Tq.
Set SJW to a range of 1 Tq to 4 Tq.
Set SS + TSEG1 + TSEG2 to a range of 8 Tq to 25 Tq.
TSEG1 > TSEG2 > SJW
