R01UH0823EJ0100 Rev.1.00
Page 1376 of 1823
Jul 31, 2019
RX23W Group
38. Serial Peripheral Interface (RSPIa)
38.3.5.2
CPHA = 1
shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1.
However, when the SPCR.SPMS bit is 1, the SSLAi signals are not used, and only the three signals RSPCKA, MOSIA,
and MISOA handle communications. In
, RSPCK (CPOL = 0) indicates the RSPCKA signal waveform
when the SPCMDm.CPOL bit is 0; RSPCKA (CPOL = 1) indicates the RSPCKA signal waveform when the CPOL bit is
1. The sampling timing represents the timing at which the RSPI fetches serial transfer data into the shift register. The I/O
directions of the signals depend on the RSPI mode (master or slave). For details, refer to
.
When the SPCMDm.CPHA bit is 1, the driving of invalid data to the MISOA signal commences at an SSLAi signal
assertion timing. The output of valid data to the MOSIA and MISOA signals commences at the first RSPCKA signal
change timing that occurs after the SSLAi signal assertion. After this timing, data is updated at every 1 RSPCK cycle.
The transfer data fetch timing is 1/2 RSPCK cycles after the data update timing. The SPCMDm.CPOL bit setting does
not affect the RSPCKA signal operation timing; it only affects the signal polarity.
t1, t2, and t3 are the same as those in the case of CPHA = 0. For a description of t1, t2, and t3 when the RSPI of this
MCU is in master mode, refer to
section 38.3.10.1, Master Mode Operation
Figure 38.23
RSPI Transfer Format (CPHA = 1)
Serial transfer period
1
2
3
4
5
6
7
8
RSPCK
cycle
Start
End
RSPCK
(CPOL = 0)
Sampling
timing
MOSI
MISO
SSLi
t1
t2
t3
RSPCK
(CPOL = 1)
RSPCKA
(CPOL = 0)
RSPCKA
(CPOL = 1)
MOSIA
MISOA
SSLAi
