R01UH0823EJ0100 Rev.1.00
Page 1384 of 1823
Jul 31, 2019
RX23W Group
38. Serial Peripheral Interface (RSPIa)
38.3.8.2
Parity Error
If full-duplex synchronous serial communications is performed with the SPCR.TXMD bit set to 0 and the SPCR2.SPPE
bit set to 1, when serial transfer ends, the RSPI checks whether there are parity errors. Upon detecting a parity error in the
received data, the RSPI sets the SPSR.PERF flag to 1. Since the RSPI does not copy the data in the shift register to the
receive buffer when the SPSR.OVRF flag is set to 1, parity error detection is not performed for the received data. To set
the PERF flag to 0, write 0 to the PERF flag after SPSR register is read with the PERF flag set to 1.
shows an example of operation of the OVRF and PERF flags. The SPSR access shown in
indicates the condition of access to SPSR register, where W denotes a write cycle, and R a read cycle. In the example of
, full-duplex synchronous serial communications is performed while the SPCR.TXMD bit is 0 and the
SPCR2.SPPE bit is 1. The RSPI performs an 8-bit serial transfer in which the SPCMDm.CPHA bit is 1 and the
SPCMDm.CPOL bit is 0. The numbers given under the RSPCKA waveform represent the number of RSPCK cycles (i.e.,
the number of transferred bits).
Figure 38.30
Operation Example of PERF Flag
The operation of the flags at the timing shown in steps (1) to (3) in the figure is described below.
(1) If a serial transfer terminates with the RSPI not detecting an overrun error, the RSPI copies the data in the shift
register to the receive buffer. The RSPI judges the received data at this timing, and sets the PERF flag to 1 if a parity
error is detected. In master mode, the RSPI copies the pointer value to SPCMDm register to the
SPSSR.SPECM[2:0] bits.
(2) If 0 is written to the PERF flag after SPSR register is read when the PERF flag is 1, the PERF flag is set to 0.
(3) When the RSPI detects an overrun error and serial transfer is terminated, the data in the shift register is not copied to
the receive buffer. The RSPI does not perform parity error detection at this timing.
The occurrence of a parity error can be checked either by reading the SPSR register or by using an RSPI error interrupt
and reading the SPSR register. When executing a serial transfer, measures should be taken to ensure the early detection
of parity errors, such as reading SPSR. When the RSPI is used in master mode, the pointer value to SPCMDm register at
the occurrence of the error can be checked by reading the SPSSR.SPECM[2:0] bits.
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
R
(3)
(1)
(2)
SPSR access
(CPHA = 1, CPOL = 0)
OVRF
W
PERF
RSPCKA
