MSC8144E Reference Manual, Rev. 3
25-30
Freescale
Semiconductor
Debugging, Profiling, and Performance Monitoring
25.2.14 Profiling Unit Programming Model
All DPU registers are memory-mapped and can be written or read by the core in Execution mode
or through the OCE Core Command in Debug mode. Only one access per execution set to a DPU
register is allowed in order to assure that the programming of the DPU registers occurs in a
deterministic order. Reserved or unused bits in all registers should be written as zeros and the
read value should be masked. Writing to unimplemented or read-only registers has no effect, and
should be avoided for future software compatibility. Reading from unimplemented or write-only
registers is illegal and produces undefined results.
Writing and reading of the DPU registers is done via the QBus. The DPU registers are located in
Bank 0. This means that there are a number of cycles until the value is actually written to the
DPU registers. In case DPU register synchronization is important, then the programming of the
last DPU register should have a SYNCIO instruction in parallel. Code following this action can
assume that the DPU registers written earlier were actually written. All registers are 32 bits with
16-bit accesses, which enable the use of bit-mask operations. When a 16-bit access is used on the
32-bit registers, the software address offset to the MSB part of the registers is equal to the
software address offset of the LSB part + 2. The LSB part of the address is as shown in the
registers memory map, and is not influenced by whether the system is Big Endian or Little
Endian.) Any other access type other than word or long (such as byte, 2 long) should be avoided,
and will result in an undefined result. When accessing the counter value registers, the 31 LSBs of
the bus are written to the 31 LSBs of the register. Bit 31 of these registers is reserved.
General Registers
— DPU Control Register (DP_CR)
— DPU Status Register (DP_SR)
— DPU Monitor Register (DP_MR)
— DPU PID Detection Reference Value Register (DP_RPID)
— DPU DID Detection Reference Value Register (DP_RDID)
General Counters
— DPU Counter Triad A Control Register (DP_TAC)
— DPU Counter Triad B Control Register (DP_TBC)
— DPU Counter A0 Control Register (DP_CA0C)
— DPU Counter A0 Value Register (DP_CA0V)
— DPU Counter A1 Control Register (DP_CA1C)
— DPU Counter A1 Value Register (DP_CA1V)
— DPU Counter A2 Control Register (DP_CA2C)
— DPU Counter A2 Value Register (DP_CA2V)
— DPU Counter B0 Control Register (DP_CB0C)
— DPU Counter B0 Value Register (DP_CB0V)
— DPU Counter B1 Control Register (DP_CB1C)
— DPU Counter B1 Value Register (DP_CB1V)
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...