MSC8144E Reference Manual, Rev. 3
18-10
Freescale
Semiconductor
QUICC Engine™ Subsystem
18.3.2.2 Selective Peripheral Recovery Procedure
Selective recovery can be a complex procedure due to the following:
The Ethernet controllers are multi-thread controllers and SNUM to peripheral/controller
translation requires maintaining association tables.
Status for multiple bus errors is not maintained, so in theory there might be additional
non-reported bus errors and the recovery will not be complete.
For these reason, a full reset and re-initialization are recommended.
18.3.3
SDMA and Reset
When the QUICC Engine subsystem is reset through the CECR[RST] bit (see the QUICC Engine
Block Reference Manual with Protocol Interworking (QEIWRM) for details), the SDMA
continues to process outstanding transactions in its FIFOs although the data related to these
transactions may be corrupted. During system reset (SRESET or HRESET), all SDMA FIFOs are
flushed and all outstanding transactions are stopped.
18.3.4
MBus Access
The SDMA requests the bus from the CLASS at two possible priority levels. When the SDMA is
in normal state, it requests the bus at priority level programmed by the user in the SDMR[EBPR]
bit field. When the SDMA is in emergency state, it requests the bus at the highest priority level
that the CLASS supports; the QUICC Engine subsystem is assigned an arbitration weight through
a field in GCR11 (see Section 8.2.27, General Control Register 11 (GCR11), on page 8-42 for
details). SDTR and SDHY program the threshold and hysteresis values that affect the conditions
for SDMA normal and emergency states. It is possible to mask the emergency state priority
requests globally in SDMR[EBMSK] and enforce the priority set in SDMR[EBPR] regardless of
the SDMA state.
The SDMA asserts the highest priority request (emergency state) for any one of the following
reasons:
When one of the FIFOs in the QUICC Engine subsystem reaches an emergency state (too
full on Rx or too empty in the middle of a frame during Tx)
When the internal SDMA data buffers are filled beyond a certain level (programmed in
SDTR/SDHY registers).
When the internal SDMA command queue is filled beyond a certain level (programmed in
SDTR/SDHY registers).
A priority request to the multi-user RAM is also asserted by the SDMA, if needed, for the same
reasons. It is possible to mask the high priority request globally in SDMR[ERMSK].
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
