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Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3

10-6

 Freescale 

Semiconductor

MSC8144E SC3400 DSP Subsystem

10.5

Interrupt Processing

The DSP core subsystem processes interrupts and exceptions generated by conditions either 
inside the SC3400 core, the DSP core subsystem modules, or external sources. In general, the 
prioritization and arbitration between the DSP core subsystem and the external interrupt sources 
is done in the Embedded Program Interrupt Controller (EPIC) module. 

The source of interrupts in the DSP core subsystem are: 

„

SC3400 core internal exceptions. The SC3400 core has several internal interrupt sources 
such as trap, illegal instruction, debug exceptions, and DALU overflow. For details on the 
SC3400 core interrupts, see the SC3400 DSP Core Reference Manual. 

„

MMU interrupts. The MMU has eight dedicated interrupt lines to the core that are treated 
as internal core interrupts even though the MMU is in the DSP core subsystem. The MMU 
itself has a number of interrupt sources, some internal to the MMU (such as protection 
violation and MATT) and some external to the MMU (such as EDC error). The MMU 
interrupts are synchronized to the core accesses and are precise interrupts. For more 
information about the MMU interrupts, see the MSC8144 SC3400 DSP Core Subsystem 
Reference Manual.

„

External interrupts. This includes interrupts generated by the MSC8144E internal 
peripherals and external interrupt input lines.

The role of the EPIC module is to manage the interrupt inputs. The EPIC manages the interrupts 
using a fixed set of priority rules and passes interrupts with the highest priority at any given time 
to the core. The EPIC also manages the acknowledgment of edge-triggered interrupts. 

The EPIC handles up to 256 interrupt inputs, including 222 interrupts external to the DSP core 
subsystem that can be independently configured as maskable or non-maskable interrupts (NMIs). 
Interrupts external to the device use the standard interrupt interface protocol.

Note:

See Chapter 13, Interrupt Handling and the MSC8144 SC3400 DSP Core Subsystem 
Reference Manual for details about interrupt processing. 

10.6

Real-Time Debug Support 

The debug support includes an internal JTAG controller and test access port (TAP), a debug and 
profiling unit (DPU), and the on-chip emulator (OCE) module. The TAP supplies the 
IEEE-specified external interface and standard JTAG debugging capability. The DPU supports 
the debugging and profiling of the DSP core subsystem in cooperation with the OCE block. The 
main debug and profiling requirements that the DPU helps support include: 

„

Cache support. Cache usage can have a significant effect on the overall performance of 
the DSP core subsystem. Application developers require observability of the internal state 
and cumulative statistics for the cache performance of their applications. 

Summary of Contents for MSC8144E

Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...

Page 2: ...rized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semic...

Page 3: ...23 26 Security Engine SEC I2C External Signals Reset Boot Program Memory Map MSC8144 SC3400 DSP Subsystem Timers Hardware Semaphores Debugging Profiling and Performance Monitoring 3 5 6 8 9 18 20 22 24 DDR SDRAM Controller 11 Interrupt Processing 12 16 QUICC Engine Subsystem Internal Memory Subsystem 10 GPIO 21 25 General Configuration Registers 17 RapidIO Interface Dedicated DMA Controller ...

Page 4: ...23 26 Security Engine SEC I2C External Signals Reset Boot Program Memory Map MSC8144 SC3400 DSP Subsystem Timers Hardware Semaphores Debugging Profiling and Performance Monitoring 3 5 6 8 9 18 20 22 24 DDR SDRAM Controller 11 Interrupt Processing 12 16 QUICC Engine Subsystem Internal Memory Subsystem 10 GPIO 21 25 General Configuration Registers 17 RapidIO Interface Dedicated DMA Controller ...

Page 5: ...Core SC3400 DSP Core 1 11 1 4 2 L1 Instruction Cache 1 12 1 4 3 L1 Data Cache 1 13 1 4 4 Memory Management Unit MMU 1 14 1 4 5 Debug and Profiling Unit DPU 1 15 1 5 Chip Level Arbitration and Switching System CLASS 1 16 1 6 Memory System 1 17 1 6 1 M2 Memory 1 17 1 6 2 M3 Memory 1 17 1 6 3 L2 Instruction Cache 1 18 1 7 Clocks 1 18 1 8 DDR Controller DDRC 1 19 1 9 DMA Controller 1 20 1 10 TDM 1 20 ...

Page 6: ...1 35 1 26 4 Application 4 1 36 1 26 5 Application 5 1 37 2 SC3400 Core Overview 2 1 Architecture 2 2 2 1 1 Data Arithmetic Logic Unit Data ALU 2 3 2 1 1 1 Data Registers 2 4 2 1 1 2 Multiply Accumulate MAC Unit 2 4 2 1 1 3 Bit Field Unit BFU 2 4 2 1 1 4 Back Trace Registers BTR 2 4 2 1 2 Address Generation Unit AGU 2 4 2 1 2 1 Stack Pointer Registers 2 6 2 1 2 2 Bit Mask Unit BMU 2 6 2 1 3 Program...

Page 7: ...G Test Access Port Signals 3 58 4 Chip Level Arbitration and Switching System CLASS 4 1 CLASS Features 4 3 4 2 Functional Description 4 4 4 2 1 Expander Module and Transaction Flow 4 4 4 2 2 Multiplexer and Arbiter Module 4 5 4 2 2 1 Atomic Stall Unit ASU 4 5 4 2 2 1 1 CLASS Arbiter 4 5 4 2 2 1 2 Weighted Arbitration 4 6 4 2 2 1 3 Late Arbitration 4 6 4 2 2 1 4 Priority Masking 4 6 4 2 2 1 5 Auto ...

Page 8: ...SS Watch Point Control Registers CnWPCR 4 32 4 7 15 CLASS Watch Point Access Configuration Register CnWPACR 4 34 4 7 16 CLASS Watch Point Extended Access Configuration Register CnWPEACR 4 36 4 7 17 CLASS Watch Point Address Mask Registers CnWPAMR 4 38 4 7 18 CLASS Profiling Time Out Registers CnPTOR 4 39 4 7 19 CLASS Target Watch Point Control Registers CnTWPCR 4 40 4 7 20 CLASS Profiling IRQ Stat...

Page 9: ...om I2C EEPROM 5 13 5 2 7 4 Loading Reduced RCW From External Pins 5 13 5 2 7 5 Hard Coded Reset Configuration Word High Fields Values 5 14 5 2 7 6 External Reset Configuration Word Low 5 15 5 2 7 7 External Reset Configuration Word High Fields Values 5 16 5 3 Reset Programming Model 5 17 5 3 1 Reset Configuration Word Low Register RCWLR 5 17 5 3 2 Reset Configuration Word High Register RCWHR 5 19 ...

Page 10: ...rs Clock Mode Register 1 DCMR1B DCMR1F 7 22 7 2 7 PLL Auxiliary Mode Register 0 PAMR0B PAMR0F 7 23 7 2 8 PLL Auxiliary Mode Register 1 PCMR1B PC1MR1F 7 24 7 2 9 PLL Auxiliary Mode Register 2 PAMR2B PAMR2F 7 24 7 2 10 Values for Reprogramming Clock Modes 7 25 8 General Configuration Registers 8 1 Programming Model 8 1 8 2 Detailed Register Descriptions 8 2 8 2 1 General Configuration Register 1 GCR...

Page 11: ...ory Map 9 7 10 MSC8144E SC3400 DSP Subsystem 10 1 SC3400 DSP Core 10 2 10 2 Memory Management Unit MMU 10 3 10 3 Instruction Channel 10 4 10 4 Data Channel and Write Queue 10 5 10 5 Interrupt Processing 10 6 10 6 Real Time Debug Support 10 6 10 7 Dual Timer 10 8 10 8 Interfaces 10 8 10 9 DSP Core Subsystem Operating States 10 8 10 9 1 Reset State 10 9 10 9 2 Execution State 10 9 10 9 3 Debug State...

Page 12: ...4 6 5 L2 ICache Line Replacement 11 14 11 4 6 5 1 PLRU Replacement 11 14 11 4 6 5 2 PLRU Bit Updates 11 15 11 4 6 5 3 PLRU Bits In Partial Lock 11 15 11 4 6 5 4 PLRU Inverse Mechanism 11 15 11 4 6 6 L2 ICache Sweep Operation 11 15 11 4 6 6 1 Invalidation Sweep 11 16 11 4 6 6 2 L2 ICache Global Sweep Operation 11 16 11 4 6 7 Fetch Operation 11 17 11 4 7 Debug Mode 11 17 11 4 7 1 Initialize Read and...

Page 13: ... 12 3 5 DDR Data Beat Ordering 12 21 12 3 6 Page Mode and Logical Bank Retention 12 22 12 4 Error Checking and Correction 12 22 12 5 Error Management 12 24 12 6 Set Up and Initialization 12 25 12 6 1 Programming Differences Between Memory Types 12 27 12 6 2 DDR SDRAM Initialization Sequence 12 29 12 7 Memory Controller Programming Model 12 30 12 7 1 Chip Select Bounds CSx_BNDS 12 32 12 7 2 Chip Se...

Page 14: ...Path Read Capture Data Low Register CAPTURE_DATA_LO 12 57 12 7 24 DDR SDRAM Memory Data Path Read Capture ECC Register CAPTURE_ECC 12 57 12 7 25 DDR SDRAM Memory Error Detect Register ERR_DETECT 12 58 12 7 26 DDR SDRAM Memory Error Disable Register ERR_DISABLE 12 59 12 7 27 DDR SDRAM Memory Error Interrupt Enable Register ERR_INT_EN 12 60 12 7 28 DDR SDRAM Memory Error Attributes Capture Register ...

Page 15: ...3 GIR3 13 21 13 5 2 6 General Interrupt Enable Register 3 for Cores 0 3 GIER3_ 0 3 13 23 14 Direct Memory Access DMA Controller 14 1 Operating Modes 14 2 14 2 Buffer Types 14 2 14 2 1 One Dimensional Simple Buffer 14 3 14 2 2 One Dimensional Cyclic Buffer 14 4 14 2 3 One Dimensional Chained Buffer 14 5 14 2 4 One Dimensional Incremental Buffer 14 6 14 2 5 One Dimensional Complex Buffers With Dual ...

Page 16: ... Mask Update Register DMAMUR 14 35 14 6 14 DMA Status Register DMASTR 14 36 14 6 15 DMA Error Register DMAERR 14 37 14 6 16 DMA Debug Event Status Register DMADESR 14 39 14 6 17 DMA Local Profiling Configuration Register DMALPCR 14 39 14 6 18 DMA Round Robin Priority Group Update Register DMARRPGUR 14 40 14 6 19 DMA Channel Active Status Register DMACHASTR 14 41 14 6 20 DMA Channel Freeze Status R...

Page 17: ...atus Configuration Register PCISCR 15 24 15 2 2 5 Revision ID Configuration Register RIDCR 15 25 15 2 2 6 Standard Programming Interface Configuration Register SPICR 15 26 15 2 2 7 Subclass Code Configuration Register SCCR 15 26 15 2 2 8 Base Class Code Configuration Register BCCCR 15 26 15 2 2 9 Cache Line Size Configuration Register CLSCR 15 27 15 2 2 10 Latency Timer Configuration Register LTCR...

Page 18: ... 0 5 PORAR 0 5 15 43 15 2 4 13 PCI Outbound Base Address Registers 0 5 POBAR 0 5 15 44 15 2 4 14 PCI Outbound Comparison Mask Registers 0 5 POCMR 0 5 15 44 15 2 4 15 Discard Timer Control Register DTCR 15 46 16 Serial RapidIO Controller 16 1 Introduction 16 2 16 1 1 Features 16 2 16 1 2 Operating Modes 16 4 16 1 3 1x 4x LP Serial Signals 16 5 16 2 RapidIO Interface Basics 16 5 16 2 1 RapidIO Trans...

Page 19: ...16 3 2 5 2 Preventing Queue Overflow in Chaining Mode 16 63 16 3 2 5 3 Switching Between Direct and Chaining Modes 16 63 16 3 2 5 4 Chaining Mode Descriptor Format 16 63 16 3 2 5 5 Chaining Mode Controller Interrupts 16 64 16 3 2 6 Software Error Handling 16 66 16 3 2 7 Hardware Error Handling 16 67 16 3 2 8 Outbound Message Controller Arbitration 16 68 16 3 3 Inbound Message Controller Operation ...

Page 20: ...Handling 16 97 16 5 8 Disabling and Enabling the Port Write Controller 16 100 16 5 9 RapidIO Message Passing Logical Specification Registers 16 100 16 6 RapidIO Programming Model 16 101 16 6 1 Device Identity Capability Register DIDCAR 16 104 16 6 2 Device Information Capability Register DICAR 16 105 16 6 3 Assembly Identity Capability Register AIDCAR 16 105 16 6 4 Assembly Information Capability ...

Page 21: ...mand and Status Register LTLACCSR 16 133 16 6 28 Logical Transport Layer Device ID Capture Command and Status Register LTLDIDCCSR 16 134 16 6 29 Logical Transport Layer Control Capture Command and Status Register LTLCCCSR 16 135 16 6 30 Port 0 Error Detect Command and Status Register P0EDCSR 16 136 16 6 31 Port 0 Error Rate Enable Command and Status Register P0ERECSR 16 137 16 6 32 Port 0 Error Ca...

Page 22: ...6 162 16 6 56 Port 0 RapidIO Outbound Window Segment 1 3 Registers 1 8 P0ROWSxRn 16 163 16 6 57 Port 0 RapidIO Inbound Window Translation Address Registers x P0RIWTARx 16 164 16 6 58 Port 0 RapidIO Inbound Window Base Address Registers x P0RIWBARx 16 165 16 6 59 Port 0 RapidIO Inbound Window Attributes Registers x P0RIWARx 16 166 16 6 60 Outbound Message x Mode Registers OMxMR 16 167 16 6 61 Outbo...

Page 23: ... Register IDQDPAR 16 195 16 6 84 Inbound Doorbell Queue Enqueue Pointer Address Registers IDQEPAR 16 196 16 6 85 Inbound Doorbell Maximum Interrupt Report Interval Register IDMIRIR 16 197 16 6 86 Inbound Port Write Mode Register IPWMR 16 198 16 6 87 Inbound Port Write Status Register IPWSR 16 199 16 6 88 Inbound Port Write Queue Base Address Register IPWQBAR 16 200 17 RapidIO Interface Dedicated D...

Page 24: ...tributes Registers DATRn 17 30 17 3 10 Destination Address Registers DARn 17 32 17 3 11 Byte Count Registers BCRn 17 33 17 3 12 Extended Next Link Descriptor Address Registers ENLNDARn 17 34 17 3 13 Next Link Descriptor Address Registers NLNDARn 17 35 17 3 14 Extended Current List Descriptor Address Registers ECLSDARn 17 36 17 3 15 Current List Descriptor Address Registers CLSDARn 17 37 17 3 16 Ex...

Page 25: ...18 7 3 Media Independent Interface MII 18 27 18 7 4 Reduced Media Independent Interface RMII Signals 18 29 18 7 5 SMII Interface 18 30 18 7 5 1 Reduced Gigabit Media Independent Interface RGMII Signals 18 31 18 7 5 2 Serial Gigabit Media Independent Interface SGMII Signals 18 33 18 7 5 2 1 SGMII Signals 18 33 18 7 6 Controlling PHY Links Management Interface 18 34 18 7 7 Ethernet Controller Initia...

Page 26: ...9 2 6 3 Threshold Pointers and Interrupts 19 26 19 2 6 4 Unified Buffer Mode 19 28 19 2 7 Adaptation Machine 19 29 19 3 TDM Power Saving 19 31 19 4 Channel Activation 19 31 19 5 Loopback Support 19 32 19 6 TDM Initialization 19 33 19 7 TDM Programming Model 19 34 19 7 1 Configuration Registers 19 36 19 7 1 1 TDMx General Interface Register TDMxGIR 19 36 19 7 1 2 TDMx Receive Interface Register TDM...

Page 27: ...lacement Register TDMxRDBDR 19 67 19 7 3 3 TDMx Transmit Data Buffer Displacement Register TDMxTDBDR 19 67 19 7 3 4 TDMx Receive Number of Buffers TDMxRNB 19 68 19 7 3 5 TDMx Transmitter Number of Buffers TDMxTNB 19 69 19 7 3 6 TDMx Receive Event Register TDMxRER 19 69 19 7 3 7 TDMx Transmit Event Register TDMxTER 19 70 19 7 3 8 TDMx Adaptation Status Register TDMxASR 19 71 19 7 3 9 TDMx Receive S...

Page 28: ...1 2 21 1 2 Timer Module Architecture 21 2 21 1 3 Setting Up Counters for Cascaded Operation 21 3 21 1 3 1 Operation of the Cascaded Timer 21 4 21 1 3 2 Cascading Restrictions 21 4 21 1 4 Timer Operating Modes 21 5 21 1 4 1 One Shot Mode 21 7 21 1 4 2 Pulse Output Mode 21 7 21 1 4 3 Fixed Frequency PWM Mode 21 7 21 1 4 4 Variable Frequency PWM Mode 21 8 21 1 5 Timer Compare Functionality 21 10 21 1...

Page 29: ... TMRnHOLDx 21 24 21 4 1 11 Timer Channel Counter Registers TMRnCNTRx 21 24 21 4 2 SC3400 DSP Core Subsystem Timers 21 24 21 4 3 Software Watchdog Timers 21 25 21 4 3 1 System Watchdog Control Register 0 4 SWCRR 0 4 21 25 21 4 3 2 System Watchdog Count Register 0 4 SWCNR 0 4 21 26 21 4 3 3 System Watchdog Service Register 0 4 SWSRR 0 4 21 27 22 GPIO 22 1 Features 22 1 22 2 GPIO Block Diagram 22 2 2...

Page 30: ... START 24 11 24 4 6 Generation of SCL When SDA Low 24 11 24 4 7 Target Mode Interrupt Service Routine 24 12 24 4 8 Target Transmitter and Received Acknowledge 24 12 24 4 9 Loss of Arbitration and Forcing of Target Mode 24 12 24 4 10 Interrupt Service Routine Flowchart 24 13 24 5 Programming Model 24 15 24 5 1 I2C Address Register I2CADR 24 15 24 5 2 I2C Frequency Divider Register I2CFDR 24 16 24 5...

Page 31: ...and Profiling 25 21 25 2 1 Features 25 21 25 2 2 Entering Debug Mode 25 22 25 2 3 Exiting Debug mode 25 22 25 2 4 SC3400 Debug and Profiling 25 23 25 2 5 L1 ICache and DCache Debug and Profiling 25 23 25 2 6 L2 ICache Debug and Profiling 25 23 25 2 6 1 CLASS Debug Profiling Units CDPU in the L2 ICache 25 24 25 2 6 2 L2 ICache Bank Profiling Events 25 25 25 2 7 DMA Controller Debug and Profiling 25...

Page 32: ...nter B1 Control Register DP_CB1C 25 54 25 2 14 17 DPU Counter B1 Value Registers DP_CB1V 25 57 25 2 14 18 DPU Counter B2 Control Register DP_CB2C 25 57 25 2 14 19 DPU Counter B2 Value Registers DP_CB2V 25 60 25 2 14 20 DPU Trace Control Register DP_TC 25 60 25 2 14 21 DPU VTB Start Address Register DP_TSA 25 64 25 2 14 22 DPU VTB End Address Register DP_TEA 25 65 25 2 14 23 DPU Trace Event Request...

Page 33: ...on EU Interface 26 7 26 1 5 Execution Units EUs 26 7 26 2 SEC Controller 26 8 26 2 1 Operation Definition and Data Control 26 8 26 2 1 1 Descriptors 26 9 26 2 1 1 1 Descriptor Structure 26 10 26 2 1 1 2 Descriptor Header 26 11 26 2 1 1 3 Descriptor Pointers 26 11 26 2 1 2 Link Tables 26 12 26 2 1 3 Using Descriptors and Link Tables 26 12 26 2 2 Assignment of EUs to Channels 26 14 26 2 2 1 Weighted...

Page 34: ...mainder Theorem 0x04 26 29 26 4 1 11 5 EC_FP_AFF_PTMULT Prime Field Elliptic Curve Scalar Point Multiply in Affine Coordinates 0x05 26 29 26 4 1 11 6 EC_F2M_AFF_PTMULT Polynomial Field Elliptic Curve Scalar Point Multiply in Affine Coordinates 0x06 26 30 26 4 1 11 7 EC_FP_PROJ_PTMULT Prime Field Elliptic Curve Scalar Point Multiply in Projective Coordinates 0x07 26 30 26 4 1 11 8 EC_F2M_PROJ_PTMUL...

Page 35: ... 2 2 DEU Key Size Register 26 38 26 4 2 3 DEU Data Size Register 26 38 26 4 2 4 DEU Reset Control Register 26 39 26 4 2 5 DEU Status Register 26 39 26 4 2 6 DEU Interrupt Status Register 26 39 26 4 2 7 DEU Interrupt Mask Register 26 39 26 4 2 8 DEU End_of_Message Register 26 39 26 4 2 9 DEU IV Register 26 40 26 4 2 10 DEU Key Registers 26 40 26 4 2 11 DEU FIFOs 26 40 26 4 3 Advanced Encryption Sta...

Page 36: ...ute 26 54 26 4 5 1 2 Dump Context 26 54 26 4 5 2 AFEU Key Size Register 26 54 26 4 5 3 AFEU Context Data Size Register 26 55 26 4 5 4 AFEU Reset Control Register 26 55 26 4 5 5 AFEU Status Register 26 55 26 4 5 6 AFEU Interrupt Status Register 26 56 26 4 5 7 AFEU Interrupt Mask Register 26 56 26 4 5 8 AFEU End_of_Message Register 26 56 26 4 5 9 AFEU Context 26 57 26 4 5 9 1 AFEU Context Memory 26 ...

Page 37: ...ter Control Register MCR 26 77 26 5 4 2 Controller Identification Register CIDR 26 79 26 5 4 3 Controller IP Block Revision Register CIPBRR 26 79 26 5 4 4 EU Assignment Status EUASR 26 80 26 5 4 5 Controller Interrupt Enable Register CIER 26 81 26 5 4 6 Controller Interrupt Status Register CISR 26 84 26 5 4 7 Controller Interrupt Clear Register CICR 26 87 26 5 5 Channel Registers and Structures 26...

Page 38: ...s DEUKR 1 3 26 123 26 5 7 11 DEU FIFOs 26 123 26 5 8 AESU Registers 26 124 26 5 8 1 AESU Mode Register AESUMR 26 124 26 5 8 2 AESU Key Size Register AESUKSR 26 126 26 5 8 3 AESU Data Size Register AESUDSR 26 127 26 5 8 4 AESU Reset Control Register AESURCR 26 128 26 5 8 5 AESU Status Register AESUSR 26 129 26 5 8 6 AESU Interrupt Status Register AESUISR 26 130 26 5 8 7 AESU Interrupt Mask Register...

Page 39: ... Key Size Register KEUKSR 26 163 26 5 11 3 KEU Data Size Register KEUDSR 26 164 26 5 11 4 KEU Reset Control Register KEURCR 26 165 26 5 11 5 KEU Status Register KEUSR 26 166 26 5 11 6 KEU Interrupt Status Register KEUISR 26 167 26 5 11 7 KEU Interrupt Mask Register KEUIMR 26 169 26 5 11 8 KEU Data Out Register KEUDOR for F9 MAC 26 171 26 5 11 9 KEU End_of_Message Register KEUEOMR 26 172 26 5 11 10...

Page 40: ...MSC8144E Reference Manual Rev 3 xl Freescale Semiconductor Contents 26 5 12 8 RNG Output FIFO 26 186 ...

Page 41: ...nd switching system CLASS Four DSP Core Subsystems Communications Memory Subsystem Includes a PCI interface serial RapidIO interface eight 512 channel 256 transmit and 256 receive TDM interfaces a UART interface an I2C interface eight timer input outputs and a QUICC Engine module with one asynchronous transfer mode UTOPIA controller two 10 100 1000Base T Ethernet controllers and an SPI In addition...

Page 42: ...anual Audience and Helpful Hints This manual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8144E It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on StarCore technology For your convenience the chapters of this manual are organized to make the informa...

Page 43: ...s in bulleted lists 0x Prefix to denote a hexadecimal number 0b Prefix to denote a binary number REG FIELD Abbreviations or acronyms for registers or buffer descriptors appear in uppercase text Specific bits fields or numeric ranges appear in brackets For example ICR INIT refers to the Force Initialization bit in the host Interface Control Register ACTIVE HIGH SIGNALS Names of active high signals ...

Page 44: ...e chapters of this manual Chapter 1 Overview Features descriptive overview of main modules configurations and application examples Chapter 2 SC3400 Core Overview Target markets features overview of development tools descriptive overview of main modules Chapter 3 External Signals Identifies the external signals lists signal groupings including the number of signal connections in each group and desc...

Page 45: ...eration of the L1 ICache L1 DCache L2 ICache M2 memory and M3 memory including the configuration programming model Chapter 12 DDR SDRAM Memory Controller Describes the how the memory controller interface works and how to program it This interface increases the efficiency of accesses through the DDR memory controller to external DDR memory Chapter 13 Interrupt Handling Discusses the interrupt contr...

Page 46: ...registers Chapter 22 GPIO Discusses the thirty two GPIO signals Sixteen of the signals can be configured as external interrupt inputs Each pin is multiplexed with other signals and can be configured as a general purpose input general purpose output or a dedicated peripheral pin Chapter 23 Hardware Semaphores Describes the function and programming of the hardware semaphores which control resource s...

Page 47: ...o the various Freescale devices Application Notes Cover various programming topics related to the StarCore DSP core and the MSC8144E device Further Reading The following documents are available with a signed non disclosure agreement see your Freescale representative or distributor for details SC3400 DSP Core Reference Manual Covers the SC3400 core architecture control registers clock registers pro...

Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...

Page 49: ...re used in the MSC81xx DSP family and the SC1400 core used in the MSC711x DSP family Each SC3400 DSP core has four ALUs and performs at 3200 4000 16 16 bit million multiply accumulates per second MMACS at 800 MHz 1 GHz yielding a maximum total performance of 12800 16000 16 16 bit MMACS per device For optimized video applications 8 8 bit multiply accumulate instructions can be used delivering a pea...

Page 50: ...gh locking flexible boundaries Software coherency support Writing policy programmable per memory segment as either write back or write through 0 25 KB write back buffer WBB Six 64 bit entry write through buffer WTB Prefetch capability Memory management unit MMU Virtual to physical address translation Task protection Multitasking Embedded programmable interrupt controller EPIC Up to 256 interrupts ...

Page 51: ...cores and other CLASS initiators to the shared M2 memory M3 memory PCI DDR SDRAM controller and the device configuration control and status registers CCSRs High bandwidth Non blocking allows parallel accesses from multiple initiators to multiple targets Fully pipelined Low latency Per target arbitration highly optimized to the target characteristics using prioritized round robin arbitration Reduce...

Page 52: ...ced Encryption Standard AES unit Implements the Rijndael symmetric key cipher ECB CBC CTR and CCM modes 128 192 and 256 bit key lengths AFEU ARC four execution unit Implements a stream cipher compatible with the RC4 algorithm 40 to 128 bit programmable key MDEU message digest execution unit SHA with 160 or 256 bit message digest MD5 with 128 bit message digest HMAC with either algorithm KEU Kasumi...

Page 53: ...gle address buffers I O device Incremental address buffers Chained buffers 1D to 4D buffers 1D or 2 4D complex buffers a combination of buffer types High bandwidth Optimized for DDR memory TDM Backward compatible with the MSC8102 MSC8122 MSC8126 TDM interface All the eight TDM modules together support up to 2K time slots for receive and 2K time slots for transmit Up to eight independent TDM module...

Page 54: ...Mbps MII one controller only 10 100 Mbps RMII consortium standard 10 100 Mbps SMII Designed to comply with the SGMII protocol using a 4 pin SerDes interface at 1000 Mbps data rate only 10 100 1000 Mbps RGMII full duplex only MAC to MAC connection in all modes Half and full duplex operations in 10 100 Mbps mode Half duplex back pressure 10 100 Mbps only Full duplex operations in 1000 Mbps mode Full...

Page 55: ...ception Supports master or slave SPI mode Supports multiple master environment Continuous transfer mode for automatic scanning of a peripheral Maximum clock rate is QUICC Engine clk 8 in master mode and QUICC Engine clk 4 in slave mode not in back to back operation Independent programmable baud rate generator Programmable clock phase and polarity Local loopback capability for testing Open drain ou...

Page 56: ...nters are preload able Compare registers can be preloaded Counters can share available inputs Separate prescaler for each counter Each counter has capture and compare capability Can use one of the following clock sources CLASS64 clock TDM clock input or external clock input Five software watchdog timer SWT modules Hardware Semaphores Eight programmable hardware semaphores locked by simple write ac...

Page 57: ...lip Chip Plastic Ball Grid Array FC PBGA 1 mm pitch 29 mm 29 mm Voltage Core nominal voltage 1 V M3 power 1 2 V I O power 1 8 V 2 5 V 3 3 V Figure 1 2 MSC8144E Block Diagram Table 1 1 MSC8144E Features Continued Feature Description JTAG RMU SRIO Note The arrow direction indicates master or slave 128 bit at DDR Interface 16 32 bit at 400 MHz data rate 8 TDMs DMA I O Interrupt Concentrator UART Cloc...

Page 58: ...tem which contains the SC3400 core the ICache the DCache the MMU for task and memory protection and address translation and two write buffers In addition there is an interrupt controller two timers a debug module and a trace write buffer The SC3400 core fetches instructions through a 128 bit wide program bus P bus and it fetches data through two 64 bit wide data buses Xa bus and Xb bus After a bri...

Page 59: ...ed data The DSP subsystem supports a Real Time Operating System RTOS as follows Virtual to physical address translation in the MMU Two privilege levels user and supervisor Memory protection The embedded programmable interrupt controller EPIC handles up to 256 interrupts with 32 priorities 222 of which are external platform inputs 1 4 1 StarCore SC3400 DSP Core The SC3400 core is a flexible program...

Page 60: ... features and the compiler friendly instruction set Even compiled pure control code yields results with high code density The SC3400 core supports general micro controller capabilities making it a suitable target for advanced operating systems These capabilities include support for user and supervisor privilege levels that enable with the off core MMU a protected software model implementation Prec...

Page 61: ...he line and the burst size is programmable through descriptors in the MMU When there is a need to fetch new data to the cache and all the ways of the matching index are valid one of the lines of the cache is thrashed into the WBB using the pseudo least recently used PLRU algorithm It is then written back into memory in programmable burst lengths Portions of the cache can be locked dynamically and ...

Page 62: ...and the physical address can assure that it executes without change after it is swapped from the DDR memory to an arbitrary location in internal MSC8144E memory Code does not depend on physical memory allocation and can be written modularly Relocatable code is not immune to addressing problems Global variables can be addressed relative to the code However in a multi core device such as MSC8144E in...

Page 63: ...signal the core to enter Debug mode The counters can be enabled and disabled by writing to their control register or by an event such as a watchpoint detected by the OCE or execution of the debug oriented core instructions MARK and DEBUGEV The counted events can be filtered so that only events that occur during a specific task marked by its task ID in the MMU are counted The main counted events ar...

Page 64: ...and Switching System CLASS The CLASS is the central interconnect system for the MSC8144E device The CLASS is a non blocking full fabric crossbar switch that gives any initiator access to any target in parallel with another initiator target couple The CLASS demonstrates per target prioritized round robin arbitration highly optimized to the target characteristics The CLASS initiators are Four SC3400...

Page 65: ...ntions between accesses The M2 memory uses SRAM technology and supports both single and burst accesses The M2 memory is fully ECC protected The M2 memory supports partial accesses Automatic Read Modify Write accesses are generated to maintain the ECC protection The M2 memory is volatile after reset 1 6 2 M3 Memory The 10 MB M3 memory can be used for both program and data and eliminates the need fo...

Page 66: ...he MSC8144E device has three input clocks A shared input clock for the system PLL core PLL and global PLL The core PLL can get an input clock either from the shared input clock or from the output of the system PLL cascaded The global PLL can get an input clock either from the shared input clock or from an input pin dedicated for PCI An input clock for the global PLL dedicated to PCI A differential...

Page 67: ...the M2 and M3 memories but also to store code In a typical application infrequently used code is either swapped into M2 M3 memory when needed or executed directly from an external DDR SDRAM The DDR SDRAM interface frequency is decoupled from the DSP subsystem frequency and it has a separate PLL to deliver the required frequency according to the bandwidth requirements It is 16 32 bits wide and can ...

Page 68: ... a total 4096 channels that are timing compliant with their clock sync and data signals The TDM is composed of eight identical and independent modules Each TDM module can be configured in one of the following modes Independent receive and transmit mode The transmitter has an input clock output data and a frame sync that can be configured as either input or output There are up to 256 transmit chann...

Page 69: ...satile communications engine based on a subset of the Freescale QUICC Engine technology that integrates several communications peripheral controllers Note See the QUICC Engine Block Reference Manual with Protocol Interworking QEIWRM for functional register and programming details The QUICC Engine module combines interface hardware and RISC firmware to support multimedia packet operations The QUICC...

Page 70: ...requency However the ability of an interface to support a sustained bit stream depends on the protocol settings and other factors Figure 1 5 shows the MSC8144E QUICC Engine module block diagram 1 11 1 Ethernet Controllers The two identical gigabit Ethernet controllers are based on the enhanced PowerQUICC II Ethernet controller with network statistics The Ethernet controllers support several standa...

Page 71: ...EOF condition is detected unless a collision within the collision window occurs in half duplex mode or an abort condition is encountered The Ethernet Controller receiver can perform pattern matching data extraction Ethernet type recognition CRC checking VLAN detection short frame checking and maximum frame length checking After a hardware reset the software driver initializes the parameter RAM and...

Page 72: ...BR over non real time ATM channels such as VBR and UBR 1 11 3 Serial Peripheral Interface SPI The serial peripheral interface SPI allows the exchange of data with other devices containing an SPI The SPI also communicates with peripheral devices such as EEPROMs real time clocks A D converters and ISDN devices The SPI is a full duplex synchronous character oriented channel that supports a four wire ...

Page 73: ...municate as follows The host may send messages to the destination MSC8144E device which are sent back to the host after processing along with a short doorbell interrupt to indicate that the packets have been processed Messages eliminate the latency of read accesses The host writes to the MSC8144E and the MSC8144E writes to the host In addition messages can be used in applications where the host do...

Page 74: ...both the receive and the transmit 1 13 2 RapidIO Messaging Unit RMU Operation The messaging unit is divided into five parts Inbound message controllers Outbound message controllers Inbound doorbell controllers Outbound doorbell controller Inbound maintenance controller The message receiver performs the following steps 1 Filters the received packets into multiple queues controllers based on selecte...

Page 75: ... the registers in the controller with the doorbell parameters doorbell data destination 2 The controller encapsulates the doorbell and transfers it to the RapidIO endpoint 3 The RapidIO endpoint sends the message 4 Acknowledges are transferred from the RapidIO endpoint to the RMU 5 Upon completion of a message the controller can send an interrupt to the SC3400 core and wait for a new sets of param...

Page 76: ... the semaphore by writing a 0 to it 1 18 Virtual Interrupts The global interrupt controller generates 32 virtual interrupts with eight interrupts per SC3400 core An interrupt is generated by a write access of each SC3400 core or by an external host CPU A virtual NMI can also be generated by a write access 1 19 I2 C Interface The inter integrated circuit I2 C controller enables the MSC8144E to exch...

Page 77: ...nd KEU perform specific mathematical manipulation required by protocols using cryptographic processing The unit is optimized to process all algorithms associated with internet protocol security IPSec internet key exchange IKE secure sockets layer transport layer security SSL TLS internet small computer system interface iSCSI secure real time transport protocol SRTP and the IEEE 802 11i security st...

Page 78: ...ta streams as they change over time By changing the visualization filter you can plot this data in a variety of ways including line charts logarithmic charts polar coordinates and scatter graphs High Speed Run Control PowerTAP high speed host target interface allows users to program in Flash ROM and cache Host Platform Support Microsoft Windows and Solaris Development Board The application develop...

Page 79: ...n V 44 V 42bis MNP5 Negotiation V 8 V 8bis HDLC Relay V 150 1 MoIP Fax Pumps V 17 V 27ter V 29 Relay T 30 FoIP T 38 Echo cancellation G 165 G 168 64 ms G 168 2004 128 ms windowed Noise reduction Acoustic level control Acoustic EC roadmap Telephony support DTMF detection Universal tone generation Special tone event detect VAD CNG PLC RTP packetization Security AES Video MPEG4 H 263 H 264 H 324MDSP ...

Page 80: ...tions covered in this section are as follows Application 1 Generic System Block Diagram Application 2 Legacy Farm Example using UTOPIA and TDM Application 3 System solution Application 4 SerDes connectivity Device Driver DMA driver Serial RapidIO driver TDM driver Ethernet driver PCI driver UTOPIA driver UART driver Memory allocation Interrupt handling Figure 1 6 Application Software Model Table 1...

Page 81: ...C8144E devices but for most applications the onboard memory is all that is required This is true of the examples that follow Figure 1 7 Generic System Block Diagram DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM TDM UTOPIA sRIO 1000Base T MSC8144E ETH sRIO ETH UTOPIA DDR I2 C TDM MSC8144E ETH sRIO ETH UTOPIA DDR I2 C TDM MSC8144E ETH sRIO ETH UTOPIA DDR I2 C TDM MSC8144E ETH sRIO ETH ...

Page 82: ...des parsing into the IP packet contained in the AAL5 cps For AAL2 it can support multiple AAL2 cps packets per cell In both cases each SC3400 core can have individual buffer rings In this example a simple TDM is chosen Figure 1 8 DSP Farm Example using UTOPIA and TDM TDM UL2 EEPROM MSC8144E ETH sRIO ETH UTOPIA DDR I2C TDM MSC8144E ETH sRIO ETH UTOPIA DDR I2C TDM MSC8144E ETH sRIO ETH UTOPIA DDR I2...

Page 83: ... switch so that the egress data path does not go through the PowerQUICC device TDM is used for the PCM side For such solutions no time slot assigner is required because the MSC8144E devices can interface with an H 110 like bus Figure 1 9 System Solution TDM MSC8144E ETH sRIO ETH UTOPIA I2C TDM MSC8144E ETH sRIO ETH UTOPIA I2 C TDM MSC8144E ETH sRIO ETH UTOPIA I2 C TDM MSC8144E ETH sRIO ETH UTOPIA ...

Page 84: ...y In this example an H 110 TDM bus is used For AMC this bus would be on the extended connector with the SerDes in the fabric area Figure 1 10 SerDes Connectivity TDM 4x 1x 1xsRIO 1xsRIO 4x 1x sRIO sRIO EEPROM MSC8144E ETH SRIO ETH UTOPIA I2 C TDM MSC8144E ETH SRIO ETH UTOPIA I2 C TDM MSC8144E ETH SRIO ETH UTOPIA I2 C TDM MSC8144E ETH SRIO ETH UTOPIA I2 C TDM MSC8144E ETH SRIO ETH UTOPIA I2 C TDM M...

Page 85: ...ver only one type of interface is required The system can self boot over either the serial RapidIO interface or Ethernet Figure 1 11 RNC Traffic Processing Board That Executes RNL Block Diagram DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM sRIO 1000Base T MSC8144E ETH sRIO ETH UTOPIA DDR I2 C TDM MSC8144E ETH sRIO ETH UTOPIA DDR I2 C TDM MSC8144E ETH sRIO ETH UTOPIA DDR I2 C TDM MSC8...

Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...

Page 87: ...ce 16 data registers 40 bits each 27 address registers 32 bits each Hardware support for fractional and integer data types Four hardware loops with zero overhead Very rich 16 bit wide orthogonal instruction set Application specific instructions for Viterbi and multimedia processing Special single instruction multiple data SIMD instructions working on 2 word or 4 byte operands packed in a register ...

Page 88: ...C3400 core can execute four multiply accumulate operations in a single clock or one MAC two arithmetic logical operations and one bit field operation All four data ALUs are identical permitting great flexibility in assigning and executing instructions increasing the likelihood that four execution units can be kept busy on any given cycle and enabling programs to take advantage of the SC3400 core p...

Page 89: ...le cycle All the MAC units and BFUs can access all the Data ALU registers Each register is partitioned into three portions two 16 bit registers low and high portion of the register and one 8 bit register extension portion The 16 bit high and low register portions are typically used as an inputs for arithmetic operations The full 40 bit register can be used as an input operand but is generally used...

Page 90: ...roduct is right justified and added to the 40 bit contents of one of the sixteen data registers 2 1 1 3 Bit Field Unit BFU The BFU contains a 40 bit parallel bidirectional shifter with a 40 bit input and a 40 bit output mask generation unit and logic unit The BFU is used in the following operations Multi bit left right shift arithmetic or logical One bit rotate right or left Bit field insert and e...

Page 91: ... registers N 0 3 Four modifier registers M 0 3 A Modifier Control Register MCTL Two Address Arithmetic Units AAU One Bit Mask Unit BMU Figure 2 2 shows a block diagram of the AGU Figure 2 2 AGU Block Diagram Program Counter PC Address R0 R1 R2 R3 R4 R5 R6 R7 N0 N1 N2 N3 NSP ESP MCTL B0 R8 B1 R9 B2 R1 B3 R1 B4 R1 B5 R1 B6 R1 B7 R1 Bit Mask Unit BMU Memory Data Bus 1 Xa_DATA Memory Data Bus 2 Xb_DAT...

Page 92: ...ftware stack two special registers with special addressing modes are assigned to the AGU the Normal Mode Stack Pointer NSP and the Exception Mode Stack Pointer ESP Both the ESP and the NSP are 32 bit read write address registers with predecrement and post increment updates as well as offset with immediate values to allow random access to the software stack Stack instructions use the ESP when the M...

Page 93: ...h target buffer BTB Reduces change of flow COF cycle latency by predicting COF resolution based on a dynamic history of previous executions of the same COF The PSEQ implements its functions using the following registers Program Counter Register PC Status Register SR Four Loop Start Address Registers SA 0 3 Four Loop Counter Registers LC 0 3 Exception and Mode Register EMR Vector Base Address Regis...

Page 94: ... addressing mode each lower bank register Rn is assigned a corresponding base address register Bn Registers B 0 7 and R 8 15 are mapped to the same physical register respectively Therefore for example R8 is available only if R0 is not being used in modulo addressing since this requires the base address register B0 See Section 2 2 2 Data Arithmetic Logic Programming Model on page 2 11 for further i...

Page 95: ...lo buffer The upper boundary of the modulo buffer is calculated by B M 1 where M is the modifier register associated with the register used When not used for modulo accessing these registers can function as alternative address registers R 8 15 Both Rx and BX 8 share the same physical register For example if R0 is not programmed for modulo addressing the base address register B0 can serve as an add...

Page 96: ...D10 h D10 I D11 D11 e D11 h D11 I D12 D12 e D12 h D12 I D13 D13 e D13 h D13 I D14 D14 e D14 h D14 I D15 D15 e D15 h D15 I ADDRESS GENERATION UNIT 31 0 R8 B0 R9 B1 R10 B2 R11 B3 R12 B4 R13 B5 R14 B6 R15 B7 31 0 N0 N1 N2 N3 M0 M1 M2 M3 MCTL 31 0 R0 R1 R2 R3 R4 R5 R6 R7 SP NSP ESP Address Registers Base Address Registers Offset and Modifier Registers PROGRAM CONTROL UNIT 31 0 PC 31 0 SR 31 0 EMR Prog...

Page 97: ... bus is replaced by a limiting constant if the value cannot be represented by the number of bits in the access width The contents of Dx are not affected if limiting occurs Only the value transferred over Xa data bus or Xb data bus is limited This process is commonly referred to as transfer saturation and it should not be confused with the arithmetic saturation mode The overflow protection is perfo...

Page 98: ...ts that reflect memory configuration servicing of a non maskable interrupt and the following exception conditions Data ALU overflow illegal execution set and illegal instruction flow The EMR GP 0 6 and BEM fields are initialized at reset as described in Table 2 1 Table 2 1 EMR GP 6 0 and BEM Field Reset Values Field Reset Value1 BEM2 1 GP0 EE1 GP1 0 GP2 ISBSEL2 from Hard Reset Configuration Word H...

Page 99: ...2 7 Move instructions are listed in Table 2 8 Stack support instructions are listed in Table 2 9 Cache instructions are listed in Table 2 10 Bit mask BMU instructions are listed in Table 2 11 Non loop change of flow non loop COF instructions are listed in Table 2 12 Loop control and loop change of flow instructions are listed in Table 2 13 Program control instructions are listed in Table 2 14 PREF...

Page 100: ...nteger data INC F Increment a data register as fractional data ISUB Integer Subtraction not affected by saturation MAX Transfer maximum signed value MAX2 Transfer two 16 bit maximum signed values MAX2VIT Special MAX2 version for Viterbi kernel MAXM Transfer maximum magnitude value MIN Transfer minimum signed value MIN2 Transfer two 16 bit minimum signed values NEG Negate NEG2 Two negate word opera...

Page 101: ...UU Multiply unsigned integer and unsigned integer first source from high portion second from low portion IMPYSU Multiply signed integer and unsigned integer IMPYSU2 Two multiply of signed by unsigned integer bytes IMPYUU Multiply unsigned integer and unsigned integer MPY Multiply signed fractions MPYR Multiply signed fractions and round MPYSU Multiply signed fraction and unsigned fraction MPYUS Mu...

Page 102: ...e Interleave BREV Bit Reverse BINTRLV Bit Interleave CLB Count leading bits ones or zeros DOALIGN Extracts unaligned four bytes EOR Logical exclusive OR EXTRACT Extract signed bit field EXTRACTU Extract unsigned bit field INSERT Insert bit field NOT One s complement inversion OR Logical inclusive OR ROL Rotate one bit left through the carry bit ROR Rotate one bit right through the carry bit SWAP S...

Page 103: ...ord operands LSRR Multiple bit logical shift right LSRR2 Multiple bit bitwise shift right of two word operands LSRR L Integer multiple bit shift right LSRW Word logical shift right 16 bit shift Table 2 7 AGU Arithmetic Instructions AAU Instruction Description ADDA Add affected by the modifier mode ADDL1A Add with 1 bit left shift of source operand affected by the modifier mode ADDL2A Add with 2 bi...

Page 104: ...ister quad MOVE B Move byte to from memory MOVE F Move fractional word to from memory MOVE L Move long to from memory MOVE W Move integer word to from memory or immediate to register or memory MOVE x Move BTR portions to memory MOVE2 2B Move two signed bytes to from memory to from a packed register MOVE2 4B Move four signed bytes to from memory to from a packed register pair MOVE2 8B Move eight si...

Page 105: ...POP 2L Pop two long register pairs from the software stack POPN Pop a register from the software stack using the normal stack pointer POPN 2L Pop two long register pairs from the software stack using the normal stack pointer PUSH Push a register onto the software stack PUSH 2L Push two long register pairs onto the software stack PUSHN Push a register onto the software stack using the normal stack ...

Page 106: ... the T bit if every bit position that has the value 1 in the mask is 1 in an operand BMTSTS W Bit mask test if set in memory Sets the T bit if every bit position that has the value 1 in the mask is 1 in an operand EOR Logical exclusive OR on a 16 bit operand NOT Binary inversion of a 16 bit operand OR Logical OR on a 16 bit operand Table 2 12 AGU Non Loop Change of Flow Instructions COF Instructio...

Page 107: ...p to start the next iteration CONTD Jump to the start of the loop to start the next iteration delayed DOENn Do enable set loop counter n and enable loop n as a long loop DOENSHn Do enable short set loop counter n and enable loop n as a short loop DOSETUPn Setup loop start address n SKIPLS Test the active LC and skip the loop if LCn is equal or smaller than zero Table 2 14 AGU Program Control Instr...

Page 108: ...an unconditional cof instruction This can be either a cof or a delayed cof instruction Table 2 15 Prefix Instructions PRE Instruction Description IFA Execute current execution set or subgroup unconditionally IFF Execute current execution set or subgroup if the T bit is clear IFT Execute current execution set or subgroup if the T bit is set NOP No operation ...

Page 109: ...multiplexed across the remaining signal lines Table 3 1 MSC8144E Functional Signal Groupings Functional Group Detailed Description Power and ground Table 3 3 on page 3 5 Clock Table 3 4 on page 3 6 Reset and Configuration Table 3 5 on page 3 7 DDR Memory Controller Table 3 6 on page 3 11 Serial RapidIO Interface Table 3 7 on page 3 12 PCI Table 3 8 on page 3 14 Ethernet Controllers Table 3 9 on pa...

Page 110: ...ltiplexing modes Table 3 2 Interface Multiplexing by Mode Interface Supported Interfaces by I O Multiplexing Mode 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 TDM TDM 0 7 TDM 0 7 TDM 0 6 TDM 0 3 TDM 0 3 TDM 0 6 TDM 0 6 TDM 0 6 PCI PCI PCI PCI no error support ATM UTOPIA8 UTOPIA16 UTOPIA8 UTOPIA8 UTOPIA8 UTOPIA16 UTOPIA8 UTOPIA16 UTOPIA8 UTOPIA8 UTOPIA16 POS Master mode Ethernet 1 SGMII MII SMII...

Page 111: ...and SMII they are 3 3 V protocols b TDM7 is not supported only 7 TDM ports are available 3 When using pin multiplexing mode 2 if the application requires the RGMII port with MDC and MDIO management done by the MSC8144E then tie VDDGE1 and VDDGE2 to a 2 5 V supply the following limitations exist a Ethernet controller 2 does not support RMII and SMII they are 3 3 V protocols b PCI is not supported t...

Page 112: ..._CLKIN_RNG TDM0RDAT SRIO_TXD2 GE1_SGMII_TX RCW_SRC0 TDM0RSYN SRIO_RXD3 GE2_SGMII_RX TDM0TCLK SRIO_RXD3 GE2_SGMII_RX RCW_SRC2 TDM0TSYN SRIO_TXD3 GE2_SGMII_TX RCW_SRC1 TDM0TDAT SRIO_TXD3 GE2_SGMII_TX TDM1RCLK TDM1 GPIO only GPIO27 SDA RC1 TDM1RSYN GPIO26 SCL RC0 TDM1RDAT GPIO24 IRQ6 TDM1TCLK GPIO23 IRQ5 RC3 TDM1TSYN GPIO22 IRQ4 RC2 TDM1TDAT GPIO21 IRQ1 GPIO16 IRQ0 QE_BRGC1 TDM2RCLK TDM2 TMR0 GPIO13 ...

Page 113: ...r source for the external non Ethernet I O signal lines Provide adequate external decoupling capacitors The external decoupling capacitors recommendations are listed in the MSC8144E Technical Data Sheet VDDGE1 Ethernet 1 Input Output Power 2 5 V or 3 3 V The power source for the Ethernet signal lines Provide adequate external decoupling capacitors The external decoupling capacitors recommendations...

Page 114: ...nd Ground dedicated for RapidIO PLL use The connection should be provided with an extremely low impedance path to ground GNDSXC RapidIO C Ground A ground for the RapidIO C circuitry Provide an extremely low impedance path to the ground plane GNDSXP RapidIO P Ground A ground for the RapidIO P circuitry Provide an extremely low impedance path to the ground plane Table 3 4 Clock Signals Signal Name T...

Page 115: ...nal requires an external pull up resistor The signal is tri stated after the soft reset flow is complete M3_RESET Input M3 Memory Reset When asserted this line causes the M3 memory to enter the reset state When using the M3 memory connect to 2 5 V using the same logic as PORESET STOP_BS Input Stop Boot Sequencer This signal is valid only when the reset configuration words are being loaded from an ...

Page 116: ... TDM 0 As an output this can be the DATA_D data signal for TDM 0 For configuration details see Chapter 20 TDM Interface RCW_SRC2 TDM0TSYN Input Input Output Reset Configuration Word Source 2 Along with the RCW_SRC 0 1 this signal is sampled at the deassertion of PORESET to identify the source of the reset configuration word The required signal level must be maintained as long as HRESET is asserted...

Page 117: ... during the assertion of PORESET to set part of the bits of the Reset Configuration Word Registers TDM2 Serial Transmitter Data The transmit data signal for TDM 2 As an output this can be the DATA_D data signal for TDM 2 For configuration details see Chapter 20 TDM Interface RC7 TDM2TSYN Input Input Output Reset Configuration Word Bit 7 Sampled during the assertion of PORESET to set part of the bi...

Page 118: ...8 Asynchronous Transfer Mode ATM Controller RC14 UTP_TPRTY Input Output Reset Configuration Word Bit 14 Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word Registers ATM UTOPIA Transmit Parity For details see Chapter 18 Asynchronous Transfer Mode ATM Controller RC15 UTP_TSOC Input Output Reset Configuration Word Bit 15 Sampled during the assertion of POR...

Page 119: ...DR SDRAM DQS Strobe for byte lane data capture The signals are inputs driven by the DDR SRAM with read data and outputs driven by the DDR controller with write data The data strobes may be single ended or differential MDQS 3 0 Input Output DDR SDRAM DQS Complement Complement strobe for byte lane data capture The signals are inputs driven by the DDR SRAM with read data and outputs driven by the DDR...

Page 120: ...e corresponding chip select Table 3 7 Serial RapidIO Signals Signal Name Type Description SRIO_IMP_CAL_RX Input SRIO Receiver Impedance Control Signal Receiver impedance calibration control signal SRIO_IMP_CAL_TX Input SRIO Transmitter Impedance Control Signal Transmitter impedance calibration control signal SRIO_RXD0 Input SRIO Receive Data 0 Serial data input for a 1x or 4x link Each signal is p...

Page 121: ...hernet 1 SGMII Transmit Data Part of the Ethernet signals For details see Chapter 20 Ethernet Controller SRIO_TXD3 GE2_SGMII_TX Output Output SRIO Transmit Data 3 Serial data output for a 4x link Each signal is part of a differential pair Ethernet 2 SGMII Transmit Data Part of the Ethernet signals For details see Chapter 20 Ethernet Controller SRIO_TXD2 GE1_SGMII_TX Output Output SRIO Transmit Dat...

Page 122: ...s data bus For details see Chapter 15 PCI ATM UTOPIA Transmit Data 8 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 2 0 1 3 4 5 6 7 PCI_AD30 GE1_TD3 UTP_TD5 Input Output Output Output PCI Address Data Line 30 Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 1 Transmit Data 3 For details see Chapter 19 Ethernet Controller ATM UTOPIA Transmit Data 5 For ...

Page 123: ...nput Output PCI Address Data Line 27 Part of the PCI address data bus For details see Chapter 15 PCI UTOPIA Transmit Address 4 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 2 0 1 3 4 5 6 7 PCI_AD27 GE1_TD0 UTP_TD2 Input Output Output Output PCI Address Data Line 27 Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 1 Transmit Data 0 For details see Chap...

Page 124: ... bus For details see Chapter 15 PCI General Purpose Input Output 7 One of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 13 One of sixteen external lines that can request a service routine via the internal interrupt controller Selected through GPIO configuration For details see Chapter 23 GPIO For functional details see Chapter 13 Interrupt Handling TDM6 Transmit Data The transmit data...

Page 125: ...terrupt Request 11 One of sixteen external lines that can request a service routine via the internal interrupt controller Selected through GPIO configuration For details see Chapter 23 GPIO For functional details see Chapter 13 Interrupt Handling TDM6 Receive Data The receive data signal for TDM 6 Selected through GPIO configuration For details see Chapter 23 GPIO For TDM configuration details see...

Page 126: ...tput Input Output PCI Address Data Line 17 Part of the PCI address data bus For details see Chapter 15 PCI General Purpose Input Output 11 One of 32 GPIOs For details see Chapter 23 GPIO TDM5 Serial Transmitter Data The transmit data signal for TDM 5 As an output this can be the DATA_D data signal for TDM 5 Selected through GPIO configuration For details see Chapter 23 GPIO For TDM configuration d...

Page 127: ... Chapter 23 GPIO For TDM configuration details see Chapter 20 TDM Interface 3 4 0 1 2 5 6 0 1 2 5 6 PCI_AD13 UTP_RCLK Input Output Input PCI Address Data Line 13 Part of the PCI address data bus For details see Chapter 15 PCI ATM UTOPIA Receive Clock For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 2 0 1 3 4 5 6 7 PCI_AD13 GPIO28 TDM5RCLK Input Output Input Output Input Output ...

Page 128: ...nterface 3 4 0 1 2 5 6 PCI_AD9 UTP_RADDR2 Input Output Input Output PCI Address Data Line 9 Part of the PCI address data bus For details see Chapter 15 PCI ATM UTOPIA Receive Address 2 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 2 0 1 3 4 5 6 7 PCI_AD9 TDM4RSYN Input Output Input Output PCI Address Data Line 9 Part of the PCI address data bus For details see Chapter 15 PCI...

Page 129: ...Carrier Sense For details see Chapter 19 Ethernet Controller 0 2 3 4 5 1 6 PCI_AD4 TDM7TSYN UTP_RMOD Input Output Input Output Input PCI Address Data Line 4 Part of the PCI address data bus For details see Chapter 15 PCI TDM7 Transmit Frame Sync Transmit frame sync for TDM 7 See Chapter 20 TDM Interface Receive Word Modulo 2 3 4 0 1 7 PCI_AD3 TDM7TDAT GE2_TD3 UTP_TMD Input Output Input Output Outp...

Page 130: ...15 PCI ATM UTOPIA Transmit Data 10 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 2 0 1 3 4 5 6 7 PCI_CBE0 GE1_TX_EN UTP_TD6 Input Output Output Output PCI Byte 0 Enable Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 1 Transmit Enable For details see Chapter 19 Ethernet Controller ATM UTOPIA Transmit Data 6 For details see Chapter 18 Asynchronous Tra...

Page 131: ...ble For details see Chapter 19 Ethernet Controller 4 0 1 2 3 5 6 PCI_CBE3 UTP_TD13 Input Output Output PCI Byte 3 Enable Part of the PCI address data bus For details see Chapter 15 PCI ATM UTOPIA Transmit Data 13 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 2 0 1 3 4 5 6 7 PCI_CBE3 GE1_RD1 UTP_RD3 Input Output Input Input PCI Byte 3 Enable Part of the PCI address data bus F...

Page 132: ...oller 3 1 2 6 0 4 5 7 PCI_PAR GPIO20 TMR4 UTP_REOP Input Output Input Output Input Output Input PCI Parity For details see Chapter 15 PCI General Purpose Input Output 20 One of 32 GPIOs For details see Chapter 23 GPIO Timer 4 The signal can be configured as an input to the counter or an output from the counter Selected through the GPIO configuration For details see Chapter 23 GPIO For timer functi...

Page 133: ...Data 3 For details see Chapter 19 Ethernet Controller ATM UTOPIA Receive Data 5 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 3 1 2 6 0 4 5 7 PCI_IRDY GPIO19 TMR3 UTP_TEOP Input Output Input Output Input Output Output PCI Ready For details see Chapter 15 PCI General Purpose Input Output 19 One of 32 GPIOs For details see Chapter 23 GPIO Timer 3 Configured as input to the cou...

Page 134: ...put PCI Device Select For details see Chapter 15 PCI General Purpose Input Output 31 One of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 3 One of sixteen external lines that can request a service routine via the internal interrupt controller Configured as part of the GPIO port For details see Chapter 23 GPIO For functional details see Chapter 13 Interrupt Handling 2 3 4 0 1 5 6 0 1 5...

Page 135: ...his can be the DATA_B data signal for TDM 7 For configuration details see Chapter 20 TDM Interface PCI Address Data Line 2 Part of the PCI address data bus For details see Chapter 15 PCI Transmit Error 5 6 0 1 2 3 4 7 GE2_TD1 PCI_CBE1 Output Input Output Ethernet 2 Transmit Data 1 For details see Chapter 19 Ethernet Controller PCI Byte 1 Enable Part of the PCI address data bus For details see Chap...

Page 136: ...2 Transmit Enable For details see Chapter 19 Ethernet Controller PCI Byte 2 Enable Part of the PCI address data bus For details see Chapter 15 PCI 0 1 2 3 5 6 7 4 GE2_TCK TDM7TCLK PCI_IDSL UTP_RER Output Input Input Input Ethernet 2 Transmit Clock For details see Chapter 19 Ethernet Controller TDM7 Transmit Clock Transmit Clock for TDM 7 For configuration details see Chapter 20 TDM Interface PCI I...

Page 137: ...ter 19 Ethernet Controller PCI Address Data Line 28 Part of the PCI address data bus For details see Chapter 15 PCI ATM UTOPIA Transmit Data 3 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 1 2 6 3 0 4 5 7 GE1_TD0 PCI_AD27 UTP_TD2 Output Input Output Output Ethernet 1 Transmit Data 0 For details see Chapter 19 Ethernet Controller PCI Address Data Line 27 Part of the PCI addre...

Page 138: ...s see Chapter 15 PCI ATM UTOPIA Transmit Data 6 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller 1 2 6 3 0 4 5 7 GE1_TX_ER PCI_CBE1 UTP_TD7 Output Input Output Output Ethernet 1 Transmit Error For details see Chapter 19 Ethernet Controller PCI Byte 1 Enable Part of the PCI address data bus For details see Chapter 15 PCI ATM UTOPIA Transmit Data 7 For details see Chapter 18 Asyn...

Page 139: ...er Mode ATM Controller 1 2 6 0 3 4 5 7 GE1_CRS PCI_AD5 Input Input Output Ethernet 1 Carrier Sense For details see Chapter 19 Ethernet Controller PCI Address Data Line 5 Part of the PCI address data bus For details see Chapter 15 PCI 1 6 0 2 3 4 5 SRIO_RXD2 GE1_SGMII_RX Input Input SRIO Receive Data 2 Serial data input for a 4x link Each signal is part of a differential pair Ethernet 1 SGMII Recei...

Page 140: ...link Each signal is part of a differential pair Ethernet 2 SGMII Transmit Data Inverted Part of the Ethernet signals For details see Chapter 20 Ethernet Controller All modes Table 3 10 UTOPIA Signals Signal Name Type Description I O Mode UTP_TD15 PCI_IRDY Output Input Output ATM UTOPIA Transmit Data 15 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Ready Part of the PCI a...

Page 141: ... Data 7 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Byte 1 Enable Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 1 Transmit Error For details see Chapter 19 Ethernet Controller 0 4 5 7 3 1 2 6 UTP_TD6 PCI_CBE0 GE1_TX_EN Output Input Output Output ATM UTOPIA Transmit Data 6 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PC...

Page 142: ... address data bus For details see Chapter 15 PCI 0 1 4 5 6 7 2 3 UTP_RD15 PCI_AD19 Input Input Output ATM UTOPIA Receive Data 15 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Address Data Line 19 Part of the PCI address data bus For details see Chapter 15 PCI 0 1 3 4 5 6 7 2 UTP_RD14 PCI_AD18 Input Input Output ATM UTOPIA Receive Data 14 For details see Chapter 18 Asynch...

Page 143: ...Input ATM UTOPIA Receive Data 6 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Parity Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 1 Receive Clock For details see Chapter 19 Ethernet Controller 0 4 5 7 3 1 2 6 UTP_RD5 PCI_IRDY GE1_RD3 Input Input Output Input ATM UTOPIA Receive Data 5 For details see Chapter 18 Asynchronous Transfer Mode ATM Co...

Page 144: ...e Chapter 15 PCI 0 1 3 4 5 6 7 2 UTP_TADDR3 Input Output ATM UTOPIA Transmit Address 3 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller All modes UTP_TADDR2 Input Output ATM UTOPIA Transmit Address 2 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller All modes UTP_TADDR1 PCI_AD24 Input Output Input Output ATM UTOPIA Transmit Address 1 For details see Chapter 1...

Page 145: ...Chapter 23 GPIO Timer 1 Configured as input to the counter or output from the counter Selected through the GPIO configuration For details see Chapter 23 GPIO For timer functional details see Chapter 22 Timers 0 1 3 5 6 7 4 2 2 UTP_TCLK PCI_AD29 Input Input Output ATM UTOPIA Transmit Clock For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Address Data Line 29 Part of the PCI ...

Page 146: ...ransfer Mode ATM Controller PCI Address Data Line 21 Part of the PCI address data bus For details see Chapter 15 PCI 0 1 3 4 5 6 7 2 UTP_TEN PCI_PAR Input Output Input Output ATM UTOPIA Transmit Enable For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Parity Part of the PCI address data bus For details see Chapter 15 PCI 0 1 3 4 5 6 7 2 UTP_REN PCI_AD20 Input Output Input Ou...

Page 147: ...or output from the counter Selected through the GPIO configuration see Chapter 22 GPIO For timer functional details see Chapter 21 Timers General Purpose Input Output 18 One of 32 GPIOs For details see Chapter 22 GPIO PCI Frame Sync For details see Chapter 15 PCI 7 0 1 2 3 5 6 0 1 2 3 5 6 4 UTP_TMD TDM7TDAT PCI_AD3 GE2_TD3 Output Input Output Input Output Output Transmit Word Modulo TDM7 Serial Tr...

Page 148: ...address data bus Ethernet 2 Receive Data 3 7 0 1 2 3 4 5 6 UTP_RVL TDM7RCLK PCI_AD0 GE2_RD2 Input Input Output Input Output Input Receive Data Valid TDM7 Receive Clock The receive clock signal for TDM 7 As an output this can be the DATA_C data signal for TDM 7 PCI Address Data Line 0 Part of the PCI address data bus Ethernet 2 Receive Data 2 7 0 1 2 3 4 5 6 UTP_TER TDM7RSYN PCI_AD2 GE2_TD2 Output ...

Page 149: ...nterrupt controller For details see Chapter 13 Interrupt Handling SPI Master Input Slave Output When the SPI is a master SPICLK is the clock input signal that shifts received data in from SPIMOSI and transmitted data out through SPIMISO GPIO22 IRQ4 SPIMOSI Input Output Input Input Output General Purpose Input Output 22 One of 32 GPIOs For details see Chapter 25 GPIO Valid in all modes Interrupt Re...

Page 150: ...e of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 2 One of the sixteen external lines that can request a service routine via the internal interrupt controller from the SC3400 core For details see Chapter 13 Interrupt Handling PCI Stop For details see Chapter 15 PCI 0 1 5 6 0 1 5 6 2 3 4 GPIO29 IRQ7 PCI_GNT Input Output Input Input General Purpose Input Output 29 One of 32 GPIOs For d...

Page 151: ...t 23 One of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 5 One of sixteen external lines that can request a service routine via the internal interrupt controller For details see Chapter 13 Interrupt Handling All modes All modes GPIO22 IRQ4 Input Output Input General Purpose Input Output 22 One of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 4 One of sixteen external lin...

Page 152: ...For details see Chapter 23 GPIO Timer 1 Configured as input to the counter or output from the counter Selected through the GPIO configuration For details see Chapter 23 GPIO For timer functional details see Chapter 22 Timers UTOPIA IR For details see Chapter 18 Asynchronous Transfer Mode ATM Controller PCI Byte Enable 3 For details see Chapter 15 PCI 2 2 0 1 3 5 6 7 4 GPIO16 IRQ0 QE_BRGC1 Input Ou...

Page 153: ...ICC Engine Baud Rate Generator Clock UTOPIA 0 For details see Chapter 18 Asynchronous Transfer Mode ATM Controller All modes All modes All modes GPIO12 TDM5TSYN PCI_AD18 Input Output Input Output Input Output General Purpose Input Output 12 One of 32 GPIOs For details see Chapter 23 GPIO TDM5 Transmit Frame Sync The transmit sync signal for TDM 5 For configuration details see Chapter 20 TDM Interf...

Page 154: ... 5 6 0 1 2 5 6 0 1 2 5 6 3 4 GPIO7 IRQ13 TDM6TDAT PCI_AD23 Input Output Input Input Output Input Output General Purpose Input Output 7 One of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 13 One of sixteen external lines that can request a service routine via the internal interrupt controller For details see Chapter 13 Interrupt Handling TDM6 Transmit Data The transmit data signal for...

Page 155: ...32 GPIOs For details see Chapter 23 GPIO Interrupt Request 10 One of sixteen external lines that can request a service routine via the internal interrupt controller For details see Chapter 13 Interrupt Handling TDM6 Receive Clock The receive clock signal for TDM 6 For configuration details see Chapter 20 TDM Interface PCI Address Data Line 19 Part of the PCI address data bus For details see Chapte...

Page 156: ...rs General Purpose Input Output 19 One of 32 GPIOs For details see Chapter 23 GPIO PCI Ready For details see Chapter 15 PCI Transmit End of Packet 0 1 2 3 5 6 0 1 2 3 5 6 4 7 TMR2 GPIO18 PCI_FRAME UTP_SRP Input Output Input Output Input Output Input Timer 2 Configured as input to the counter or output from the counter Selected through the GPIO configuration For details see Chapter 23 GPIO For time...

Page 157: ...terrupt Handling All modes All modes All modes URXD RC_LDF GPIO14 IRQ8 Input Output Output Input Output Input UART Receive Data Selected through the GPIO configuration For details see Chapter 23 GPIO For functional details see Chapter 21 UART Reset Configuration Word Load Failure Used by the core to signal when the reset configuration word fails to load from an I2 C EEPROM when using the boot sequ...

Page 158: ...ription I O Mode TDM7TDAT PCI_AD3 GE2_TD3 UTP_TMD Input Output Input Output Output Output TDM7 Serial Transmitter Data The serial transmit data signal for TDM 7 As an output it provides the DATA_D signal for TDM 7 For configuration details see Chapter 20 TDM Interface PCI Address Data Line 3 Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 2 Transmit Data 3 For details see ...

Page 159: ...s an input this can be the DATA_B data signal for TDM 7 For configuration details see Chapter 20 TDM Interface PCI Address Data Line 2 Part of the PCI address data bus For details see Chapter 15 PCI Ethernet 2 Transmit Data 2 For details see Chapter 19 Ethernet Controller Transmit Error 0 1 2 3 4 5 6 7 TDM6TDAT GPIO7 IRQ13 PCI_AD23 Input Output Input Output Input Input Output TDM6 Transmit Data Th...

Page 160: ...face General Purpose Input Output 5 One of 32 GPIOs For details see Chapter 23 GPIO Interrupt Request 11 One of sixteen external lines that can request a service routine via the internal interrupt controller Selected through the GPIO port see Chapter 23 GPIO For functional details see Chapter 13 Interrupt Handling PCI Address Data Line 20 Part of the PCI address data bus For details see Chapter 15...

Page 161: ...Address Data Line 17 Part of the PCI address data bus For details see Chapter 15 PCI 0 1 2 5 6 0 1 2 5 6 3 4 TDM5TCLK PCI_AD16 Input Input Output TDM5 Transmit Clock Transmit Clock for TDM 5 For configuration details see Chapter 20 TDM Interface PCI Address Data Line 16 Part of the PCI address data bus For details see Chapter 15 PCI 0 1 2 5 6 3 4 TDM5TSYN GPIO12 PCI_AD18 Input Output Input Output ...

Page 162: ...nal details see Chapter 20 TDM Interface PCI Address Data Line 11 Part of the PCI address data bus For details see Chapter 15 PCI 0 1 2 5 6 3 4 TDM4TCLK PCI_AD10 Input Input Output TDM4 Transmit Clock Transmit clock for TDM 4 For configuration details see Chapter 20 TDM Interface PCI Address Data Line 10 Part of the PCI address data bus For details see Chapter 15 PCI 0 1 2 5 6 3 4 TDM4TSYN PCI_AD1...

Page 163: ...an input this can be the DATA_A data signal for TDM 3 For configuration details see Chapter 20 TDM Interface Reset Configuration Word Bit 8 Used to load part of the Reset Configuration Word during Reset All modes Reset TDM3RCLK RC16 Input Output Input TDM3 Receive Clock The receive clock signal for TDM 3 As an output this can be the DATA_C data signal for TDM 3 For configuration details see Chapte...

Page 164: ...on Word during Reset All modes Reset TDM1TDAT RC2 Input Output Input TDM1 Serial Transmitter Data The transmit data signal for TDM 1 As an output this can be the DATA_D data signal for TDM 1 For configuration details see Chapter 20 TDM Interface Reset Configuration Word Bit 2 Used to load part of the Reset Configuration Word during Reset All modes Reset TDM1TCLK Input TDM1 Transmit Clock Transmit ...

Page 165: ... Chapter 20 TDM Interface Reset Configuration Word Source 2 Along with the RCW_SRC 0 1 this signal is sampled at the deassertion of PORESET to identify the source of the reset configuration word All modes Reset TDM0RDAT RCFG_CLKIN_RNG Input Output Input TDM0 Serial Receiver Data The receive data signal for TDM 0 As an input this can be the DATA_A data signal for TDM 0 For configuration details see...

Page 166: ...he MSC8144E internal interrupt controller Assertion of this output indicates that a non maskable interrupt is pending in the MSC8144E internal interrupt controller waiting to be handled by an external host Table 3 18 JTAG TAP Signals Signal Name Type Signal Description EE0 Input OCE Event Bit 0 Used for putting the internal SC3400 cores into Debug mode Pulling the signal high asserts the signal an...

Page 167: ...OCE Event and JTAG Test Access Port Signals MSC8144E Reference Manual Rev 3 Freescale Semiconductor 3 59 ...

Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...

Page 169: ...ized trade off between power dissipation memory technology and miss latency Controlling the intradevice data flow the CLASS reduces bottle necks and permits high bandwidth fully pipe lined traffic The CLASS system is ready for use and does not require any special configuration to perform non blocking pipelined transactions from any initiator to any memory The configurable arbitration features desc...

Page 170: ...e MSC8144E Device PCI DDR CCSR M2 M2 M2 M2 M3 Extended DMA Controller L2 QUICC Serial TDM PCI ICache Data Bus Chip Level Arbitration and Switching System CLASS Core0 Extended Data Bus Core1 Extended Data Bus Core2 Extended Data Bus Core3 Port 0 Port 1 Port 2 Port 3 Controller Controller Controller Controller Target Devices Initiator Devices RapidIO Engine Subsystem DMA L2 ICache CLASS0 CLASS1 CLAS...

Page 171: ...on Fixed priority between address decoding results which allows overlapping address windows and deduction of address windows Bank address interleaving is supported for ports 1 4 on CLASS0 M2 Ports 0 3 are interleaved every 256 bytes meaning that address bits 9 8 provide access to ports 1 4 of CLASS0 Per target arbitration algorithm 4 level prioritization Each level implements pseudo round robin ar...

Page 172: ...actions For more details about normalizer module see Section 4 2 3 The MSC8144E device CLASS modules support different bus widths numbers of initiator devices and number of target devices Table 4 1 lists the characteristics of the three CLASS modules 4 2 1 Expander Module and Transaction Flow Each expander module connects to one initiator The expander module performs address decoding according to ...

Page 173: ...nd checks to see whether it is appropriate to modify some bits and ends when the initiator gets the end of transaction signal for write atomic access The ASU includes an Atomic Open flag which is set when an initiator receives the acknowledge for its read atomic access While the Atomic Open flag is set all the read atomic accesses from other initiators are stalled When the atomic operation ends th...

Page 174: ...5 CLASS Arbitration Control Register CnACR 4 2 2 1 4 Priority Masking When CnACR PME is set the class arbiters are configured to preserve cycle slots for low priority accesses They reserve 1 16 of all cycles for priority 0 2 16 of all cycles for priority 1 or 0 and 2 16 of all cycles for priority 2 1 or 0 This mode can decrease overall performance This is one of two approaches to eliminate starvat...

Page 175: ...ampler for full pipeline towards the target The normalizer module is the only module within the CLASS that can manipulate the transaction for example splitting non aligned transactions An internal signal is used to indicate that optimization is needed Only the last normalizer module on the way to the target is used for normalization All the other normalizer modules should be used only as samplers ...

Page 176: ...and report the error In case of a read transaction the CLASS delivers invalid data to the initiator If at the time of the error transaction there are open transactions that did not receive the end of transaction the expander module stalls all new transaction until all prior transactions receive the end of transaction close the error transaction report the end of transaction report the error and on...

Page 177: ...CPCR PE bit Configuring a watch point event in CPCR WPEC field The CDPU is deactivated by Writing a 0 to the CPCR PE bit Configuring a watch point event in CPCR WPEC field Reaching a time out in the CPTOR when the CPCR TOE bit is set CPRCR overflow After the desired profiling mode has been chosen activate the CDPU to perform the measurement At the beginning of every measurement the CLASS Profiling...

Page 178: ...f the watch point events If you use the watch point events to enable disable the profiling unit according to WPCE clear this bit 7 After the measurement are finished check the following registers Read the CnPISR OVE bit In time out mode read CnPRCR If CnPISR OVE is set or if CnPRCR is equal to CnPTOR the results are not valid Read CnPGCRx to get the number of watch point events during the measurem...

Page 179: ...on Supervisor Initiator Bandwidth 0 00 00111 Initiator Read Data Ack Initiator Write Data Ack Initiator target Bandwidth 0 00 10000 T Initiator Target T Read Data Ack Initiator Target T Write Data Ack Arbitration Winner Priority 0 0 01 00000 Target T Win Priority 0 Target T Win Priority 1 Target T Win Priority 2 Target T Win Priority 3 Target Access Splitting 0 1 01 00000 Target T Initiator Access...

Page 180: ...ds of reset Synchronous hard reset Synchronous soft reset 4 5 1 Soft Reset This kind of reset has the following effects All the CLASS state machines return to their idle state All the CLASS operation FFs return to their idle state The CLASS configuration registers are reset as described in the table for each register in Section 4 7 Programming Model 4 5 2 Hard Reset This reset brings all states ma...

Page 181: ...not allow more than one open atomic access per target When an atomic access is open toward a particular target all the other atomic accesses are stalled until the first atomic access toward that target is completed Note Atomic operations are only supported in M2 memory and not in any other memory Arbitration Performance Only the CLASS1 arbiter has a wasted cycle only at transition from high priori...

Page 182: ...e Registers see page 4 28 CLASS Target Profiling Configuration Registers see page 4 29 CLASS Profiling Control Registers see page 4 31 CLASS Watch Point Control Registers see page 4 32 CLASS Watch Point Access Configuration Registers page 4 34 CLASS Watch Point Extended Access Configuration Registers see page 4 36 CLASS Watch Point Address Mask Registers see page 4 38 CLASS Profiling Time Out Regi...

Page 183: ...ngs 31 28 0 Reserved Write to 0 for future compatibility IGN 27 0 Ignore Write Confirmation Indicates whether to use real confirmation or ignore confirmation fast confirmation These bits are used together as follows 000 Initiator sends specified confirmation and target uses real confirmation mode 001 Initiator sends specified confirmation and target uses specified confirmation mode 010 Initiator s...

Page 184: ...size PB 20 0 Power Burst Controls power burst power of two Notes 1 The normalizer only generates accesses to the target that meet the burst requirements specified by BA FSB and PB values 2 BA FSB and PB are not implemented for CLASS2 and these bits are reserved in the CLASS2 registers 19 0 Reserved Write to 0 for future compatibility MBS 18 16 0 Max Burst Size Represents the maximum byte count the...

Page 185: ...00 Disabled 001 2 datums 010 4 datums 011 8 datums 100 16 datums 101 32 datums 110 64 datums 111 128 datums 7 4 0 Reserved Write to 0 for future compatibility RC 3 0 0 Response Control Because accesses can be segmented and have a few target accesses the end of transmission EOT attributes are accumulated The normalizer has four bits that defined the accumulated EOT attributes This bit defines the m...

Page 186: ...s the priority value assigned to transactions that arrive with a value of 3 00 Priority 0 01 Priority 1 10 Priority 2 11 Priority 3 11 10 0 Reserved Write to 0 for future compatibility PM2 9 8 10 Priority Mapping 2 Holds the priority value assigned to transactions that arrive with a value of 2 00 Priority 0 01 Priority 1 10 Priority 2 11 Priority 3 7 6 0 Reserved Write to 0 for future compatibilit...

Page 187: ...ade Value Registers Offset 0x840 x 0x04 C1PAVR 0 5 C2PAVR 0 3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AUV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 5 CnPAVRx Bit Descriptions Name Reset Description 31 16 0 Reserved Write to 0 for future compatibility AUV 15 0 0 Auto Upgrade Value The v...

Page 188: ... Auto Upgrade Control Registers Offset 0x880 x 0x04 C1PACR 0 5 C2PACR 0 3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AUE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 6 CnPACRx Bit Descriptions Name Reset Description Settings 31 1 0 Reserved Write to 0 for future compatibility AUE 0 0 Auto Up...

Page 189: ...ions Note The generated interrupts correspond to the following sources C1EAR0 Address generated by one of the 4 cores on the data bus or DMA port 0 C1EAR1 Address generated by DMA port 1 C1EAR2 Address generated by one of the 4 cores on the instruction bus or the L2 ICache C1EAR3 Address generated by a QUICC Engine peripheral C1EAR4 Address generated by the RapidIO controller TDM or PCI inbound C1...

Page 190: ...ns C1EEAR 0 4 CLASS 1 Extended Error Address Registers Offset 0x9C0 x 0x04 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RW Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA AA SRC_ID ERR_ADD Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 8 C1EEARx Bit Descriptions Name Reset Description Settings 31 17 0 Reserved Write to 0 for future compatibili...

Page 191: ...ache Core 1 0x06 L2 ICache Core 2 0x07 L2 ICache Core 3 0x08 DMA Port 0 0x09 0x10 reserved 0x11 QUICC Engine subsystem 0x12 RapidIO interface 0x13 reserved 0x14 TDM interface 0x15 PCI controller 0x16 0x17 reserved 0x18 DMA port 1 0x19 0x1F reserved ERR_ADD 3 0 0 Error Address This field stores the 4 msbs of the address of the internal transaction that caused the error Table 4 8 C1EEARx Bit Descrip...

Page 192: ...d descriptions C0IPCR 0 5 CLASS Initiator Profiling Configuration Registers Offset 0xA00 x 0x04 C1IPCR 0 5 C2IPCR 0 2 3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMM Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 9 CnIPCRx Bit Descriptions Name Reset Description Settings 31 5 0 Reserved Write...

Page 193: ...Module Initiator Number Initiator Module CLASS0 CLASS1 CLASS2 0 DSP core subsystem 0 CLASS0 Serial RapidIO 1 DSP core subsystem 1 DMA Controller PCI Controller 2 DSP core subsystem 2 L2 ICache TDM 3 DSP core subsystem 3 QUICC Engine subsystem 4 DMA Controller CLASS2 5 CLASS1 C0IWPCR 0 5 CLASS Initiator Watch Point Control Registers Offset 0xA40 x 0x04 C1IWPCR 0 5 C2IWPCR 0 3 Bit 31 30 29 28 27 26 ...

Page 194: ...gher priority request instead of the weighted winner Table 4 12 lists the CnAWRx bit field descriptions C0AWR 0 5 CLASS Arbitration Weight Registers Offset 0xA80 x 0x04 C1AWR 0 5 C2AWR 0 3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WEIGHT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 12 CnAWR...

Page 195: ...tatus Register Offset0xD80 C1ISR C2ISR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AEI5 AEI4 AEI3 AEI2 AEI1 AEI0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 13 CnISR Bit Descriptions Name Reset Description Settings 31 6 0 Reserved Write to 0 for future compatibility AEI 5 0 5 0 0 Address Err...

Page 196: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AEIE5 AEIE4 AEIE3 AEIE2 AEIE1 AEIE0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 14 CnIER Bit Descriptions Name Reset Description Settings 31 6 0 Reserved Write to 0 for future compatibility AEIE 5 0 5 0 0 Address Error Interrupt Enable Used to enable dis...

Page 197: ...action Therefore only one PMM field in CnIPCRx and CnTPCR can be greater than 0 during profiling Table 4 15 lists the CnTPCR bit field descriptions C0TPCR CLASS Target Profiling Configuration Register Offset 0xE00 C1TPCR C2TPCR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TT TN PMM Type R W Reset 0 0 0 ...

Page 198: ...3 011 PCI Controller 100 CLASS0 101 111 Reserved For CLASS2 000 CLASS1 001 111 Reserved 7 2 0 Reserved Write to 0 for future compatibility PMM 1 0 0 Profiling Measurement Mode Selects the profiling measurement for the selected target If TT 0 00 No profiling measurement 01 Arbitration winner priority measurement 10 Collisions measurement 11 reserved If TT 1 00 No profiling measurement 01 Transactio...

Page 199: ...0 0 0 0 0 0 0 Table 4 16 CnPCR Bit Descriptions Name Reset Description Settings 31 10 0 Reserved Write to 0 for future compatibility WPEC 9 8 0 Watch Point Event Configuration Controls the effects of a Watch Point Unit event 00 No effect 01 Assertion of watch point event sets PE 10 Assertion of watch point event clears PE 11 Assertion of watch point event toggles PE 7 5 0 Reserved Write to 0 for f...

Page 200: ...e write with confirm type comparison 0 Write with confirm type compare disabled 1 Write with confirm type compare with CnWPEACR enabled EATE 14 0 EOT Attributes Compare Enable Enables disables the EOT attributes comparison 0 EOT attributes compare disabled 1 EOT attributes compare with CnWPEACR enabled ATE 13 0 Attributes Compare Enable Enables disables the attributes comparison 0 Attributes compa...

Page 201: ... test type comparison 0 Test type compare disabled 1 Test type compare with CnWRACR enabled SPVE 3 0 Supervisor Access Compare Enable Enables disables supervisor access comparison 0 Supervisor type compare disabled 1 Supervisor type compare with CnWRACR enabled RWE 2 0 Read Write Compare Enable Enables disables read write type comparison 0 Read write type compare disabled 1 Read write type compare...

Page 202: ... 7 6 5 4 3 2 1 0 ADDR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 18 CnWPACR Bit Descriptions Name Reset Description Settings ATR 31 0 Atomic Result Defines the atomic result type to monitor 0 Atomic access failed 1 Atomic access succeeded ATA 30 0 Atomic Access Defines the atomic access type to monitor 0 Non atomic access 1 Atomic access RS 29 0 Read Safe Access Defines the read safe a...

Page 203: ...2 This field along with the ADDM field in CnWPAWMR defines the start and range of the addresses the watch point unit monitors Note For every bit in CnWPAMR ADDM that is cleared make sure the corresponding bit is cleared in the ADDR The bit location in ADDM b corresponds to the b 12 bit location in ADDR Table 4 18 CnWPACR Bit Descriptions Continued Name Reset Description Settings ...

Page 204: ...0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI PR BC Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 19 CnWPEACR Bit Descriptions Name Reset Description Settings UP 31 0 Upgradeable Access Defines the upgradeable access type to monitor 0 Non upgradeable access 1 Upgradeable access WC 30 0 Write with Confirm Access Defines the write with confirm access type to monitor 0 Fast ...

Page 205: ... L2 ICache Core2 0x07 L2 ICache Core3 0x11 QUICC Engine module 0x18 DMA port 1 Other values equal to the initiator source ID point to CLASS2 For CLASS2 0x12 RapidIO interface 0x14 TDM interface 0x15 PCI controller PR 10 9 0 Priority Defines the priority level to monitor 00 Priority 0 highest 01 Priority 1 10 Priority 2 11 Priority 3 lowest BC 8 0 0 Byte Count This field defines the value of the by...

Page 206: ... 0 0 0 0 0 0 0 0 0 0 0 Table 4 20 CnWPAMR Bit Descriptions Name Reset Description Settings 31 8 0 Reserved Write to 0 for future compatibility ADDM 7 0 0 Address Mask Defines the range and alignment of the address to monitor if address monitoring is enabled The start address is defined in CnWPACR ADDR Note For every bit in ADDM that is cleared make sure the corresponding bit is cleared in the CnWP...

Page 207: ...rofiling counters The register is reset only by a hardware reset Table 4 21 lists the CnPTOR bit field descriptions C0PTOR CLASS Profiling Time Out Registers Offset 0xE18 C1PTOR C2PTOR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TO Type R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TO Type R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 4 21 CnPTOR Bit...

Page 208: ... M2 port 0 Target 2 is M2 port 1 Target 3 is M2 port 2 Target 4 is M2 port 3 C0TWPCR CLASS Target Watch Point Control Registers Offset 0xE1C C1TWPCR C2TWPCR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WPEN5 WPEN4 WPEN3 WPEN2 WPEN1 WPEN0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 22 CnTWPCR ...

Page 209: ...ardware reset or by setting the appropriate CnCPCR PE bit Table 4 23 lists the CnPISR bit field descriptions C0PISR CLASS Profiling IRQ Status Registers Offset 0xE20 C1PISR C2PISR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WPE OVE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 23 CnPISR Bit De...

Page 210: ...pe R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WPEE OVEE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 24 CnPIER Bit Descriptions Name Reset Description Settings 31 2 0 Reserved Write to 0 for future compatibility WPEE 1 0 Watch Point Event Enable Enables disables a watch point interrupt 0 Watch point interrupt is masked 1 Watch point interrupt is e...

Page 211: ...ing measurement or during the watch point unit operation The counter starts counting from zero when the profiling unit is enabled The CnPRCR stops when the profiling unit is disabled or when the CnPRCR reaches the value stored in CnPTOR and CnCPCR TOE is set which causes the CLASS to clear the CnCPCR PE bit to disable the profiling unit When CnCPCR PE clears the CLASS stops all profiling counters ...

Page 212: ...uture compatibility PMDRD 2 0 PCI Master Delayed Read Disable Selects the method of outbound read transactions When delayed reads are enabled the PCI controller issues new read transactions only after the previous read is completed on the bus If set together with the PPE bit the PCI controller can cascade read transactions to a single stream The bit can only be set when the PCI controller is worki...

Page 213: ...mory C0ACR CLASS Arbitration Control Registers Offset 0xFC0 C1ACR C2ACR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PME Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LA5 LA4 LA3 LA2 LA1 LA0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 28 CnACR Bit Descriptions Name Reset Description Settings 31 29 0 Reserved Write to 0 for future compati...

Page 214: ...iptions Note Never write to these registers when there are open transactions being handled by the CLASS to the specified target controlled by the register C1SAD1 CLASS1 Start Address Decoders Offset 0xC00 x 0x04 C1SAD2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 Type R W Reset SAD1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 SAD2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 ...

Page 215: ... controlled by the register C1EAD1 CLASS1 End Address Decoders Offset 0xC40 x 0x04 C1EAD2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EA35 EA34 EA33 EA32 EA31 EA30 EA29 EA28 Type R W Reset EAD1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 EAD2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EA27 EA26 EA25 EA24 EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 Type R ...

Page 216: ... ensure proper operation do not enabled the specific decoder before the start and end addresses are specified in the associated C1SADx and C1EADx These registers are reset by a hardware reset only Table 4 23 lists the C1ATDx bit field descriptions Note Never write to these registers when there are open transactions being handled by the CLASS to the specified target controlled by the register C1ATD...

Page 217: ...ng the reset sequence This section describes the various ways to reset and configure the MSC8144E device 5 1 Reset Operations The MSC8144E has several inputs to the reset logic Power on reset PORESET External hard reset HRESET External soft reset SRESET Software watchdog reset JTAG reset RapidIO reset Software hard reset Software soft reset All of these reset sources are fed into the reset control...

Page 218: ...ources Name Description Power on reset PORESET Input pin Asserting this pin initiates the power on reset flow that resets all the device and configures various attributes of the device including its clock modes Hard reset HRESET This is a bidirectional I O pin The MSC8144E can detect an external assertion of HRESET only if it occurs while the MSC8144E is not asserting reset During HRESET SRESET is...

Page 219: ...uration word low load the system PLL PLL0 begins to lock When the system PLL PLL0 is locked the clock unit starts distributing clock signals in the device When all clocks are locked and the reset configuration words are loaded HRESET is released SRESET is released sixteen clocks later Note The M3_RESET signal should use the PORESET signal timing External reset logic should deassert M3_RESET and PO...

Page 220: ...loading the reset configuration words Loading time depends on the reset configuration word source 6 Once Reset Configuration Word Low is loaded the system PLL PLL0 begins to lock 7 The device keeps driving HRESET low until all PLLs are locked and the reset configuration words are loaded 8 Deassert the optional HRESET if not done earlier There is no need to assert SRESET when HRESET is asserted 9 T...

Page 221: ...tion Min 32 CLKIN cycles Device is ready End loading reset configuration words Duration depends on source Start loading reset configuration words stable clock CLKIN PORESET TRST SRESET HRESET Reset Configuration Reset Configuration input output output input input signals Words loading PLLs are locked no external indication Min 32 CLKIN cycles Device is ready End loading reset configuration words D...

Page 222: ...ng the presence of an external hard soft reset Figure 5 3 shows a timing diagram of the hard reset flow Note Because the MSC8144E does not sample the reset configuration signals during a hard reset flow changing the levels of these signals from the values samples during a HRESET sequence has no effect 5 1 6 SRESET Flow The SRESET flow is initiated externally by asserting SRESET or internally when ...

Page 223: ...oaded from these sampled inputs are accessible to software through memory mapped registers described in Section 5 3 3 They are used to configure the device operation 5 2 2 Reset Configuration Words Source The reset configuration words source RCW_SRC 0 2 options permit the MSC8144E to load reset configuration words from an EEPROM via the I2 C interface a combination of external pins and hard coded ...

Page 224: ...s signal can help debug reset issues 5 2 5 Selecting Reset Configuration Input Signals Table 5 3 shows how to pull down 0 or pull up 1 the reset configuration input signals for various configurations The reset sequence duration is measured from the deassertion of PORESET to the deassertion of SRESET Note When loading the RCW from I2 C RCWHR ER must be set 1 Table 5 3 Selecting Reset Configuration ...

Page 225: ...ection 5 3 Reset Configuration Word Low Register RCWLR Reset Configuration Word High Register RCWHR Reset Status Register RSR Note See Section 5 3 for register details 5 2 7 Loading The Reset Configuration Words The MSC8144E loads the reset configuration words from an I2 C serial EEPROM or combination of default values and external pins or uses a hard coded configuration as selected by the reset c...

Page 226: ... to the 0b1010000 address The EEPROM device must have address inputs connected to GND in multi device reset applications No additional EEPROMs are accessed by the boot sequencer in reset configuration mode See also Section 5 2 7 2 Loading Multiple Devices From a Single I2C EEPROM on page 5 11 5 2 7 1 3 EEPROM Data Format In Reset Configuration Mode The I2C module expects a specific data format in ...

Page 227: ...he first stage of reset configuration the reset initiator reads its own reset configuration words It accesses the I2 C EEPROM while all other reset targets are stopped When PORESET is deasserted the STOP_BS is latched in the reset block after few cycles and defines the reset initiator and targets It also keeps all the reset target I2 C controllers in idle state while the reset initiator starts to ...

Page 228: ...laced by a redundant device 5 2 7 2 2 Multiple Device ROM Code The multiple device scheme allows ROM code to support a number of devices loading from the same serial EEPROM target The routine flow is described in Section 6 4 1 Multi Device Support for the I2 C Bus on page 6 5 Figure 5 4 Multi Device I2C Reset Configuration Hardware HRESET PORESET I2 C EPROM STOP_BS SDA SCL SDA SCL VDD VDD SRESET C...

Page 229: ...iguration word from external pins RC 0 16 The other bits of the RCWs are loaded from default hard coded word The hardware connection is shown in Figure 5 6 Table 5 2 defines the Hard Coded Reset Configuration Word Low fields values according to RCW_SRC 0 2 Figure 5 5 Single Device I2C Reset Configuration Figure 5 6 External Pins Reduced Reset Configuration Table 5 4 Hard Coded Reset Configuration ...

Page 230: ...2 7 0 Enable core PLL PLL1 6 0 Enable system PLL PLL0 5 0 001011 for RCW_SRC 100 001011 for RCW_SRC 101 110101 for RCW_SRC 110 110101 for RCW_SRC 111 MODCK 5 0 Table 5 5 Hard Coded Reset Configuration Word High Fields Values Bits RCW_SRC 0 2 1xx Meaning 31 0 Reserved 30 0 No reset targets to be configured 29 0 Watch Dog Timer is disabled 28 23 000010 for RCW_SRC 1x0 001000 for RCW_SRC 1x1 000010 B...

Page 231: ...011 Meaning 31 30 00 Select clock number 2 for CLK0 29 26 0000 Reserved 25 0 SerDes filter select 24 0 Reserved 23 0 RapidIO VDD is 1 V 22 20 001 RapidIO SGMII reference clock is 100 MHz SerDes 1 25 GHz 19 RC 16 RC 3 0 RapidIO disabled on SerDes 1 RapidIO enabled on SerDes 18 RC 16 0 RapidIO 4x protocol 1 RapidIO 1x protocol 17 RC 16 0 Disable SGMII1 on SerDes 1 Enable SGMII1 on SerDes 16 RC 16 RC...

Page 232: ... 30 0 No reset targets to be configured 29 0 Watch Dog Timer is disabled 28 0 Boot port select 5 27 26 RC 15 14 Boot port select 4 3 25 0 Boot port select 2 24 23 RC 13 12 Boot port select 1 0 See Table 5 10 22 1 Reserved 21 1 Rapid IO host access enabled 20 15 01_1000 RapidIO prescale timer enabled OCeaN clock is 200 MHz 14 0 Reserved 13 12 00 Pins multiplexing 3 2 11 10 RC 11 10 Pins multiplexin...

Page 233: ...e RCWLR bit fields RCWLR Reset Configuration Word Low Register Offset 0x00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLKO SF RV SCLK RIOE 1x SGMII1 SGMII2 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPCI SDDR SM3 GPD CPD SPD MODCK Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5 8 RCWLR Bit Descriptions Name Reset Description Settings CLKO 3...

Page 234: ...d on SerDes SGMII1 17 0 SGMII 1 Enable 0 SGMII 1 is disabled on SerDes 1 SGMII 1 is enabled on SerDes SGMII2 16 0 SGMII 2 Enable 0 SGMII 2 is disabled on SerDes 1 SGMII 2 is enabled on SerDes 15 13 0 Reserved Write to zero for future compatibility SPCI 12 0 Select System PLL PLL0 for PCI Clock 0 Select global PLL PLL2 for PCI 1 Select system PLL PLL0 for PCI SDDR 11 0 Select System PLL PLL0 for DD...

Page 235: ...number of reset targets is defined externally 0 Reset target 1 Reset initiator EWDT 29 Enable Watchdog Timer Selects the status of the software watchdog when coming out of reset The user can override this value by writing a 1 to the System Watchdog Control Register SWCRR SWEN during system initialization 0 Watchdog timer initially disabled 1 Watchdog timer initially enabled BPRT 28 23 Boot Port Se...

Page 236: ...rt type is small system 1 Common transport type is large system Table 5 10 Boot Port Select Field Name Boot Port Value Binary Description BPRT PCI 000000 PCI with no DDR 000001 PCI using single DDR 32 Mbytes 000010 PCI default DDR 256 Mbytes 000011 PCI using single DDR 64 Mbytes 000100 PCI using single DDR 128 Mbytes 000101 PCI using DDR 512 Mbytes 000110 Reserved 000111 Reserved I2 C 001000 I2 C ...

Page 237: ...rce 000 Reserved 001 I2 C EEPROM with CLKIN less than 44 MHz or from 66 100 MHz 010 I2 C EEPROM with CLKIN of 44 66 MHz or more than 100 MHz 011 Input pins and default settings 100 Hard coded option 1 101 Hard coded option 2 110 Hard coded option 3 111 Hard coded option 4 28 24 0 Reserved Write to zero for future compatibility RIO 23 0 Hard Reset from RapidIO Indicates whether the RapidIO interfac...

Page 238: ... requested 7 4 0 Reserved Write to zero for future compatibility SW4 3 0 Software Watchdog Timer 4 Indicates whether software watchdog timer 4 has expired 0 Software watchdog timer 4 not expired 1 Software watchdog timer 4 expired SW0 2 0 Software Watchdog Timer 0 Indicates whether software watchdog timer 0 has expired 0 Software watchdog timer 0 not expired 1 Software watchdog timer 0 expired SRS...

Page 239: ...le writes to the RCR write a 1 to the RCER CRE bit Table 5 12 defines the bit fields of RPR RPR Reset Protection Register Offset 0x18 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RCPW Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCPW Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5 12 RPR Bit Descriptions Name Reset Description RCPW 31 0 0 R...

Page 240: ...Settings 31 3 0 Reserved Write to zero for future compatibility SHR 2 0 Soft Hard Reset Setting this bit cause the MSC8144E to convert all hard reset flows to soft reset flows This feature can be used for debug This bit returns to its reset state during the reset sequence so reading it always returns a 0 0 Normal hard reset flow 1 Hard reset flow converted to soft reset flow SWHR 1 0 Software Hard...

Page 241: ...0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 5 14 RCER Bit Descriptions Name Reset Description Settings 31 1 0 Reserved Write to zero for future compatibility CRE 0 0 Control Register Enabled Indicates the status of the reset control register RC...

Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...

Page 243: ...ode services the watchdog timer if the EWDT bit in the reset configuration word high register RCWHR is set recommended If the boot process fails EE1 is configured as a debug acknowledge output and the core writes an indication of the root error cause to address 0xC007B004 in M2 memory see Section 6 8 Boot Errors on page 6 22 for details The boot program does not configure the DDR controller Theref...

Page 244: ...al time to complete initialization Core 0 generates a read transaction towards M3 uses the transaction completion as the end of the M3 initialization and then allows the bootloader to place code in the M3 memory Boot mode select core 0 This part includes downloading of code from one of the MSC8144E bootable ports as defined by the RCWHR BPRT field Boot completion All cores complete the boot operat...

Page 245: ...U Control Register M_CR Note The EPIC L1 ICache and MMU are part of the SC3400 DSP core subsystem See the the MSC8144 SC3400 DSP Core Subsystem Reference Manual for configuration details The manual is only available with a signed non disclosure agreement NDA Contact your Freescale sales office or representative for more information 6 3 M3 Initialization Delay The boot code reads the GSR M3_EXIST b...

Page 246: ... the number of lines equals the number of slaves For up to 15 slaves using glue logic to drive the STOP_BS signals the number of required lines is equal to If RCWLR ERIO is set LCSBA1CSR is set to 0x1FFE0000 thereby allowing the configuration register space to be physically mapped This allows configuration and maintenance of the registers through regular read and write operations rather than by ma...

Page 247: ...r RCWHR RM 2 For each EEPROM there can be 0 or more EEPROM slaves An EEPROM slave is defined as a device that reads is RCW from the EEPROM and uses data on the bus during boot The number of EEPROM slaves is stored as a single byte at address 0x8F of the EEPROM 3 For each EEPROM there can be 0 or more reset slaves A reset slave is defined as a device that only reads its RCW from the EEPROM but does...

Page 248: ... the sequence of driving the RCW to the reset slaves the core goes into a debug state and writes the appropriate error code to the M2 memory see Section 6 8 6 4 2 Example Configuration Figure 6 2 describes a I2C multi device system in which MSC8122 0 is a reset master and MSC8122 1 is a reset slave The reset master uses GPIO 0 3 GPIO 21 to release the reset slaves The MSC8144 boot supports up to 1...

Page 249: ...onductor 6 7 Figure 6 2 I2 C Multi Device System HRESET PORESET I2C EPROM STOP_BS SDA SCL SDA SCL VDD VDD SRESET CFG_CLKIN_RNG RCW_SRC MSC8144E Device 0 3 HRESET PORESET STOP_BS SDA SCL SRESET CFG_CLKIN_RNG RCW_SRC MSC8144E Device 1 3 GPIO VDD Decoder Reset Logic A 0 2 ...

Page 250: ...ecoded STOP_SLV_BS 0 No Write freq division ratio sampling rate RCWLR MODCK need to reach 400 KHz numSlaves 5 Yes No Last Slave No RSR RSTSRC 1 Read slave RCW and generate STOP 2 Configure I2 C controller to emulate EEPROM with address 0x57 1 Reload time out counter 2 Drive corresponding slave RCWs 3 Disable time out counter RCWHR RM RCWHR BPRC I2C No Yes End of flow No Yes No Yes All STOP_BS 1 RC...

Page 251: ...ssible to 400 kHz b The Reset master reads the slaves RCW into M2 c The I2 C is configured to work as an EEPROM slave mode with address 0x57 d The MSC8144E deassert STOP_BS for the current slave directly or via the decoder e Drive preamble 0xAA55AA Drive header 0xFFFFFF Drive RCWLR Drive header 0xFFFFFF Drive RCWHR Disable the I2 C controller in order to free it up as the slaves I2 C controller do...

Page 252: ...CWHR DEVID The expected format is consecutive 6 byte fields Serial RapidIO configuration This option allows the user to configure up to 481 registers and should be used to set the appropriate values of RIO_CR and SGMII_CR in the general configuration block The expected format is address data pairs After the last such pair if there are less than 48 the address field should be set to 0xFFFFFFFF to s...

Page 253: ... Reset Configuration Word High 31 24 0x000E Reset Configuration Word High 23 16 0x000F Reset Configuration Word High 15 8 0x0010 Reset Configuration Word High 7 0 0x0011 Number of Reset Slaves 0x0012 Reset Configuration Word Low 31 24 Reset Configuration Word Low of Slave 1 0x0013 Reset Configuration Word Low 23 16 0x0014 Reset Configuration Word Low 15 8 0x0015 Reset Configuration Word Low 7 0 0x...

Page 254: ...te 0x020F Configuration Last Byte Device 0x2F Last MAC Address Byte 0x0210 1 0 1 1 1 1 1 1 Block Control Block 0 0x0211 size 31 24 Block Size 0x0212 size 23 16 0x0213 size 15 8 0x0214 NBA 31 24 Next Block Address 0x0215 NBA 23 16 0x0216 NBA 15 8 0x0217 NBA 7 0 0x0218 DA 31 24 Destination Address 0x0219 DA 23 16 0x021A DA 15 8 0x021B DA 7 0 CODE Payload Data Checksum 15 8 Checksum and Checksum Chec...

Page 255: ...should be cleared 0 6 bits of CHIP_ID indicate the destination chip 0x3F means broadcast 2 Block Size These 3 bytes represent the number of bytes in the payload data field e g if the payload size is 12 bytes Block Size 0x00 0x00 0x0C 3 Next Block Address The address in which the next block is located If the next block address equals 0x0 the bootloader assumes that the next block is sequential If n...

Page 256: ...START condition The I2 C slave drives its data beginning with the Block Control byte until the end of the block The last byte of each block is not acknowledged by the MSC8144 After the ninth unacknowledged bit the boot code generates a STOP condition Figure 6 6 describes the Software I2C read access 6 5 2 Ethernet The MSC8144E device can load files through the Ethernet port using DHCP Dynamic Host...

Page 257: ...knowledge to the TFTP server 6 Repeating steps 2 5 until the end of the data is transferred Table 6 1 Ethernet Boot Availability by I O Multiplexing Mode Multiplexing Mode RGMII RMII SMII SGMII 0 Not supported Not supported If RCWLR SGMII1 1 Ethernet booting is supported Otherwise it is not supported 1 Supported Supported 2 Supported Supported 3 Not supported Not supported 4 Not supported Not supp...

Page 258: ...cast message to the client There are two possibilities for setting the MSC8144E MAC address during the boot User defined and read from an I2 C EEPROM See Section 6 5 1 for details Predefined default using the following fields A constant of 24 bits 0x1E 0xF7 0xD5 8 bits consisting of RCWHR DEVID aligned to the right and padded with 0 A constant of 16 bits 0x00 0x00 The predefined option is configur...

Page 259: ...e client handshakes each data block by issuing a TFTP ACK allowing the server to proceed with subsequent TFTP DATA messages This process repeats until all data blocks are received 6 5 2 3 Boot File Format The Ethernet bootloader expects an application file in the form of an S Record file The S Record file is a text representation of the binary program code The S Record file structure is describes ...

Page 260: ...data S7 Record Termination record The address fields is interpreted as the 4 byte address to which to jump after boot Shown below is a typical S record format file S0030000FC S30D00002FE731DC3180BEF09E7062 S705000000000C The S0 record is comprised as follows S0 Indicating it is a starting record 03 Hexadecimal 03 decimal 3 Indicating that three character pairs or ASCII bytes follow 0000 Informatio...

Page 261: ...ecord line includes an address field that maps the lines data content to a memory location in MSC8122 Core 0 moves the data to this address Note Because the MSC8144E uses 32 bit addressing use of S3 and S7 is recommended 6 5 3 Serial RapidIO Interconnect In this procedure a Serial RapidIO master waits for the MSC8122 boot program to finish its default initialization and then initializes the device...

Page 262: ... address data pairs 6 5 4 PCI In this procedure a PCI HOST waits for the MSC8122 boot program to finish its default initialization and then initializes the device by typically loading code and data to the internal memory Before enabling the PCI Host the boot code configures 3 PCI address inbound windows as follows 1 Inbound window 0 maps a window of 512 KB starting at address 0xC0000000 which cons...

Page 263: ... see the same data format used for the I2 C EEPROM see Section 6 5 1 I2 C EEPROM on page 6 10 item 4 for details on the boot code requirements starting at address 0 of the SPI A shared SPI bus is arbitrated by all the devices connected to it by polling CS All signals should be connected as open drain if more than one device is connected to the SPI flash The SPI bus will run no faster than 400 KHz ...

Page 264: ...easons are listed in Table 6 3 Table 6 3 Boot Error Codes Error Code Description 0x003FEFFF Catastrophic Error SmartDSP OS Function failed 0x003FEFFD Corrupted boot file The possible causes are Checksum wrong in TFTP file Checksum wrong in I2 C file Unsupported S Record type 0x003FEFFC TFTP server time out 0x003FEFFB Empty frame from TFTP server 0x003FEFFA TFTP server sent ERROR code 05 0x003FEFF9...

Page 265: ...e clocks that are distributed to the system blocks The clock circuits are locked according to the selected clock mode when the first stage of the system reset configuration is done reset configuration is controlled by the RESET block Figure 7 1 MSC8144E Clock Scheme CLKIN DIV PLL1 Core PLL PLL0 System PLL PLL DIV DIV DIV DIV PLL DIV DIV DIV DIV PLL DIV DIV PLL2 Global PLL serdes PLL PCI_CLK_IN Ser...

Page 266: ...us clock to the CLKIN input 2 The ratio between the PCI clock frequency and external PCI bus clock frequency must be one of the following 2 1 3 1 4 1 5 1 or 6 1 3 The CLASS64 clock frequency must be greater than or equal to the PCI clock frequency 4 The CLASS128 clock frequency must be greater than or equal to the M3 frequency Use the following formula to calculate a specific clock frequency FJ Ta...

Page 267: ...itional settings It then controls the locking of the clock generation circuits PLL dividers and so forth and synchronizes the output clocks to the input clock 7 1 1 Clock Modes The clock logic supports several pre defined clock modes as described in Table 7 2 Table 7 3 Table 7 4 Table 7 5 and Table 7 6 The clock circuits are locked by the time that the first stage of the reset configuration is com...

Page 268: ...5 1 3 0 1 0 36 1 6 0 1 0 37 1 3 0 1 0 38 1 6 0 1 0 39 1 6 0 1 0 40 1 6 0 1 0 41 1 3 0 1 0 42 1 6 0 1 0 43 1 6 0 1 0 44 1 4 0 1 0 45 1 4 0 1 0 46 1 2 0 1 0 47 1 2 0 1 0 48 1 4 0 1 0 49 1 2 0 1 0 50 1 2 0 1 0 51 1 4 0 1 0 52 1 2 0 1 0 53 1 12 0 0 0 54 1 12 0 0 0 55 1 12 0 0 0 56 1 12 0 0 0 57 1 10 0 0 0 58 1 8 0 0 0 59 1 6 0 1 0 60 1 5 0 1 0 61 1 1 1 0 1 62 1 1 1 0 1 63 1 1 1 0 1 Table 7 2 Clock Mod...

Page 269: ... 0 0 0 0 13 2 6 0 0 1 0 14 1 12 0 0 0 0 15 1 2 0 0 1 0 16 1 12 0 0 0 0 17 1 6 0 0 0 0 18 1 12 0 0 0 0 19 1 2 0 0 1 0 20 1 2 0 0 1 0 21 1 12 0 0 0 0 22 1 2 0 0 1 0 23 1 12 0 0 0 0 24 1 12 0 0 0 0 25 1 6 0 0 0 0 26 1 2 0 0 1 0 27 1 2 0 0 1 0 28 1 15 0 0 0 0 29 2 5 0 0 1 0 30 1 15 0 0 0 0 31 1 8 0 0 0 0 32 1 15 0 0 0 0 33 2 5 0 0 1 0 34 2 5 0 0 1 0 35 1 8 0 0 0 0 36 1 15 0 0 0 0 37 1 8 0 0 0 0 38 2 5...

Page 270: ... 0 0 62 1 1 0 1 0 0 63 1 2 0 0 1 0 Table 7 4 Clock Modes PLL2 MODE PCMR2 PD MF BYP CAS EQ DLY 0 1 5 0 0 0 1 1 5 0 0 0 2 1 8 0 0 0 3 1 8 0 0 0 4 1 12 0 1 1 5 1 12 0 1 1 6 1 12 0 1 1 7 1 12 0 1 1 8 1 8 0 0 0 9 1 8 0 0 0 10 1 5 0 0 0 11 1 5 0 0 0 12 1 6 0 0 0 13 1 6 0 0 0 14 1 4 0 1 1 15 1 4 0 1 1 16 1 10 0 1 1 17 1 10 0 1 1 18 1 5 0 1 1 19 1 10 0 1 1 20 1 5 0 1 1 21 1 6 0 1 1 22 1 6 0 1 1 23 1 16 0 ...

Page 271: ... 0 1 1 37 1 6 0 1 1 38 1 6 0 1 1 39 1 16 0 1 1 40 1 8 0 1 1 41 1 8 0 1 1 42 1 16 0 1 1 43 1 8 0 1 1 44 1 6 0 1 1 45 1 6 0 1 1 46 1 6 0 1 1 47 1 6 0 1 1 48 1 6 0 1 1 49 1 6 0 1 1 50 1 6 0 1 1 51 1 6 0 1 1 52 1 8 0 1 1 53 1 10 0 1 1 54 1 12 0 1 1 55 1 16 0 1 1 56 1 12 0 1 1 57 1 12 0 1 1 58 1 12 0 1 1 59 1 12 0 1 1 60 1 12 0 1 1 61 1 1 1 1 1 62 1 1 1 1 1 63 1 1 1 1 1 Table 7 4 Clock Modes PLL2 Conti...

Page 272: ...2 1 1 1 15 1 2 4 1 2 1 1 1 16 1 2 4 1 2 1 1 1 17 1 2 4 1 2 1 1 1 18 1 2 4 1 2 1 1 1 19 1 2 4 1 2 1 1 1 20 1 2 4 1 2 1 1 1 21 1 2 4 1 2 1 1 1 22 1 2 4 1 2 1 1 1 23 1 2 4 1 2 1 1 1 24 1 2 4 1 2 1 1 1 25 1 2 4 1 2 1 1 1 26 1 2 4 1 2 1 1 1 27 1 2 4 1 2 1 1 1 28 1 2 4 1 2 1 1 1 29 1 2 4 1 2 1 1 1 30 1 2 4 1 2 1 1 1 31 1 2 4 1 2 1 1 1 32 1 2 4 1 2 1 1 1 33 1 2 4 1 2 1 1 1 34 1 2 4 1 2 1 1 1 35 1 2 4 1 2...

Page 273: ... 4 1 2 1 1 1 Table 7 6 Clock Modes Dividers for Clocks 8 12 MODE CK8DF CK9DF CK10DF CK11DF CK12DF 0 1 8 5 1 1 1 1 8 5 1 1 2 1 8 4 1 1 3 1 8 4 1 1 4 1 8 2 1 1 5 1 8 2 1 1 6 1 8 2 1 1 7 1 8 2 1 1 8 1 8 4 1 1 9 1 8 4 1 1 10 1 8 5 1 1 11 1 8 5 1 1 12 1 8 2 1 1 13 1 8 2 1 1 14 1 8 2 1 1 15 1 8 2 1 1 16 1 8 5 1 1 17 1 8 5 1 1 18 1 8 5 1 1 19 1 8 5 1 1 20 1 8 5 1 1 21 1 8 2 1 1 22 1 8 2 1 1 23 1 8 4 1 1 ...

Page 274: ... 1 40 1 8 4 1 1 41 1 8 4 1 1 42 1 8 4 1 1 43 1 8 4 1 1 44 1 8 2 1 1 45 1 8 2 1 1 46 1 8 1 1 1 47 1 8 1 1 1 48 1 8 1 1 1 49 1 8 1 1 1 50 1 8 1 1 1 51 1 8 1 1 1 52 1 8 4 1 1 53 1 8 5 1 1 54 1 8 2 1 1 55 1 8 4 1 1 56 1 8 2 1 1 57 1 8 2 1 1 58 1 8 2 1 1 59 1 8 2 1 1 60 1 8 2 1 1 61 1 8 1 1 1 62 1 8 1 1 1 63 1 8 1 1 1 Table 7 6 Clock Modes Dividers for Clocks 8 12 Continued MODE CK8DF CK9DF CK10DF CK11...

Page 275: ... the front registers Register values for each clock mode are listed in Table 7 13 Clock Mode Register Reprogramming Values on page 7 25 Note The values listed for PCMR0 assume that the GP_CTL field 000 This field can be changed subject to the restrictions in this chapter 2 Set SCCR RLKPLL and SCCR RLKDIV to activate the new settings Note Setting the SCCR RLKPLL and SCCR RLKDIV bits activates the r...

Page 276: ...ock registers is 0xFFF24000 7 2 1 System Clock Control Register SCCR The SCCR stores the general configuration of the system clocks It is initialized only by a power on reset Table 7 7 defines the SCCR bit fields SCCR System Clock Control Register Offset 0x000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RLK PLL RLK DIV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 ...

Page 277: ...k 3 Disable Used to disable clock 3 to conserve power 0 Clock 3 enabled 1 Clock 3 disabled CLK4DIS 11 0 Clock 4 Disable Used to disable clock 4 to conserve power 0 Clock 4 enabled 1 Clock 4 disabled CLK5DIS 10 0 Clock 5 Disable Used to disable clock 5 to conserve power 0 Clock 5 enabled 1 Clock 5 disabled CLK6DIS 9 0 Clock 6 Disable Used to disable clock 6 to conserve power 0 Clock 6 enabled 1 Clo...

Page 278: ...The reset value is determined by the value of MODCK bits See Table 7 13 on page 7 25 for a summary by mode Table 7 8 PCMR0 Bit Descriptions Name Reset Description Settings PD 31 28 X PLL Predivider Defines the PLL predivider division factor 0000 PD 1 0001 PD 2 0010 PD 3 0011 PD 4 0100 PD 5 0101 PD 6 0110 PD 7 0111 PD 8 1000 PD 9 1001 PD 10 1010 PD 11 1011 PD 12 1100 PD 13 1101 PD 14 1110 PD 15 111...

Page 279: ...he RCFG_CLKIN_RNG input at the deassertion of PORESET 0 CLKIN 25 to 66 MHz 1 CLKIN 66 to 133 MHz EQDLY 18 X Use Equivalent Delay Feedback Loop Determines the type of feedback loop used by the PLL 0 Use short path System clocks are positive edge aligned to CLKIN with non zero delay 1 Use equivalent delay path System clocks are positive edge aligned to CLKIN with zero delay 17 3 X Reserved GP_CTL 2 ...

Page 280: ...X X X X X X X X X X Note The reset value is determined by the value of MODCK bits See Table 7 13 on page 7 25 for a summary by mode Table 7 9 PCMR1 Bit Descriptions Name Reset Description Settings PD 31 28 X PLL Predivider Defines the PLL predivider division factor 0000 PD 1 0001 PD 2 0010 PD 3 0011 PD 4 0100 PD 5 0101 PD 6 0110 PD 7 0111 PD 8 1000 PD 9 1001 PD 10 1010 PD 11 1011 PD 12 1100 PD 13 ...

Page 281: ...L1 disabled BYP 20 X PLL0 Bypass Used to bypass PLL1 0 PLL1 is not bypassed 1 PLL1 is bypassed CAS 19 X PLL Cascade Cascades PLL1 with PLL0 so that the output of PLL0 is the input to PLL1 0 Input is CLKIN 1 Input is PLL0 output cascaded EQDLY 18 X Use Equivalent Delay Feedback Loop Determines the type of feedback loop used by the PLL 0 Use short path System clocks are positive edge aligned to CLKI...

Page 282: ...eset value is determined by the value of MODCK bits See Table 7 13 on page 7 25 for a summary by mode Table 7 10 PCMR2 Bit Descriptions Name Reset Description Settings PD 31 28 X PLL Predivider Defines the PLL predivider division factor 0000 PD 1 0001 PD 2 0010 PD 3 0011 PD 4 0100 PD 5 0101 PD 6 0110 PD 7 0111 PD 8 1000 PD 9 1001 PD 10 1010 PD 11 1011 PD 12 1100 PD 13 1101 PD 14 1110 PD 15 1111 PD...

Page 283: ...2 is not bypassed 1 PLL2 is bypassed CAS 19 X PLL Cascade Cascades PLL2 with PCI input clock or system CLKIN 0 PLL2 input is CLKIN 1 PLL2 input is PCI_CLK_IN EQDLY 18 X Use Equivalent Delay Feedback Loop Determines the type of feedback loop used by the PLL 0 Use short path System clocks are positive edge aligned to CLKIN with non zero delay 1 Use equivalent delay path System clocks are positive ed...

Page 284: ...value of MODCK bits See Table 7 13 on page 7 25 for a summary by mode Table 7 11 DCMR0 Bit Descriptions Name Reset Description Settings CK0DF 31 28 X CK0 Division Factor Defines the division factor for clock 0 0000 CK0DF 1 0001 CK0DF 2 0010 CK0DF 3 0011 CK0DF 4 0100 CK0DF 5 0101 CK0DF 6 0110 CK0DF 7 0111 CK0DF 8 1000 CK0DF 9 1001 CK0DF 10 1010 CK0DF 11 1011 CK0DF 12 1100 CK0DF 13 1101 CK0DF 14 111...

Page 285: ...ines the division factor for clock 5 0000 CK5DF 1 0001 CK5DF 2 0010 CK5DF 3 0011 CK5DF 4 0100 CK5DF 5 0101 CK5DF 6 0110 CK5DF 7 0111 CK5DF 8 1000 CK5DF 9 1001 CK5DF 10 1010 CK5DF 11 1011 CK5DF 12 1100 CK5DF 13 1101 CK5DF 14 1110 CK5DF 15 1111 CK5DF 16 CK6DF 7 4 X CK6 Division Factor Defines the division factor for clock 6 0000 CK6DF 1 0001 CK6DF 2 0010 CK6DF 3 0011 CK6DF 4 0100 CK6DF 5 0101 CK6DF ...

Page 286: ...s See Table 7 13 on page 7 25 for a summary by mode Table 7 12 DCMR1 Bit Descriptions Name Reset Description Settings CK8DF 31 28 X CK8 Division Factor Defines the division factor for clock 8 0000 CK8DF 1 0001 CK8DF 2 0010 CK8DF 3 0011 CK8DF 4 0100 CK8DF 5 0101 CK8DF 6 0110 CK8DF 7 0111 CK8DF 8 1000 CK8DF 9 1001 CK8DF 10 1010 CK8DF 11 1011 CK8DF 12 1100 CK8DF 13 1101 CK8DF 14 1110 CK8DF 15 1111 CK...

Page 287: ... CK11DF 8 1000 CK11DF 9 1001 CK11DF 10 1010 CK11DF 11 1011 CK11DF 12 1100 CK11DF 13 1101 CK11DF 14 1110 CK11DF 15 1111 CK11DF 16 CK12DF 15 12 X CK12 Division Factor Defines the division factor for clock 12 0000 CK12DF 1 0001 CK12DF 2 0010 CK12DF 3 0011 CK12DF 4 0100 CK12DF 5 0101 CK12DF 6 0110 CK12DF 7 0111 CK12DF 8 1000 CK12DF 9 1001 CK12DF 10 1010 CK12DF 11 1011 CK12DF 12 1100 CK12DF 13 1101 CK1...

Page 288: ...egister as PAMR2F The reset value is determined by the MODCK bits in the reset configuration word low Settings from this field are used only during relock as defined in Table 7 13 on page 7 25 PAMR1B PLL Auxiliary Mode Register 1 Offset 0x064 PAMR1F Offset 0x074 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PAMR1 Type B F R W Reset X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 ...

Page 289: ...000046FF 0x0000C6FF 0x000046FF 20 0x01301000 0x07400000 0x028BC000 0x008B4000 0x020FC000 0x000046FF 0x0000C6FF 0x000046FF 21 0x01301000 0x07100000 0x028BC000 0x05834000 0x028F8000 0x000046FF 0x0000C6FF 0x000046FF 22 0x01301000 0x07100000 0x028BC000 0x008B4000 0x028F8000 0x000046FF 0x0000C6FF 0x000046FF 23 0x01301000 0x07300000 0x028BC000 0x05834000 0x078F8000 0x000046FF 0x0000C6FF 0x000046FF 24 0x...

Page 290: ...x000046FF 0x0000C6FF 0x000046FF 54 0x01301000 0x07100000 0x0583C000 0x008B4000 0x058F8000 0x000046FF 0x0000C6FF 0x000046FF 55 0x01301000 0x07300000 0x0583C000 0x008B4000 0x078F8000 0x000046FF 0x0000C6FF 0x000046FF 56 0x01301000 0x07100000 0x0583C000 0x120B4000 0x058F8000 0x000046FF 0x0000C6FF 0x000046FF 57 0x01304000 0x07100000 0x0483C000 0x010B4000 0x058F8000 0x000046FF 0x0000C6FF 0x000046FF 58 0...

Page 291: ... see page 8 6 DDR General Control Register DDR_GCR see page 8 7 RapidIO Control Register RIO_CR see page 8 8 SGMII Control Register SGMII_CR see page 8 9 QUICC Engine Control Register QECTLR see page 8 10 GPIO Input Enable Register GIER see page 8 11 System Part and Revision ID Register SPRIDR see page 8 12 General Configuration Register 4 GCR4 see page 8 13 General Interrupt Register 1 GIR1 see p...

Page 292: ...Bit 7 6 5 4 3 2 1 0 TDM_PIPE_LMT Type R W Reset 0 0 0 1 0 0 0 0 Table 8 1 GCR1 Bit Descriptions Name Reset Description Settings 31 22 0 Reserved Write to 0 for future compatibility M2M_DDRC_IM 21 0 M2M DDRC Init Mode Enable Enables disables the DDR controller init mode 0 Init mode disabled 1 Init mode enabled 20 17 0 Reserved Write to 0 for future compatibility UART_STOP 16 0 UART Stop Stops the U...

Page 293: ...ription Settings 31 7 0 Reserved Write to 0 for future compatibility DMA_DBG 8 0 DMA Debug Mode Request When set initiates a request for the DMA controller to enter Debug mode See Section 14 6 16 DMA Debug Event Status Register DMADESR on page 14 39 0 No request 1 DMA debug request CORE3_STP_EN 7 0 Core 3 Stop Enable Enables core 3 subsystem to stop 0 Stop disabled 1 Stop enabled CORE2_STP_EN 6 0 ...

Page 294: ... 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CORE3_STP_ ACK CORE2_STP_ ACK CORE1_STP_ ACK CORE0_STP_ ACK Type R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CORE3_DBG _STS CORE2_DBG _STS CORE1_DBG _STS CORE0_DBG _STS Type R Reset 0 0 0 0 0 0 0 0 Table 8 3 GSR1 Bit Descriptions Name Reset Description Settings 31 29 0 Reserved Write to 0 for future compatibility M3_EXIST 28 0 M3 Exists and Has Power Indicates ...

Page 295: ...ether core 3 subsystem is stopped 0 Core subsystem not stopped 1 Core subsystem stopped CORE2_STP_ACK 10 0 Core 2 Stop Acknowledge Reflects whether core 2 subsystem is stopped 0 Core subsystem not stopped 1 Core subsystem stopped CORE1_STP_ACK 9 0 Core 1 Stop Acknowledge Reflects whether core 1 subsystem is stopped 0 Core subsystem not stopped 1 Core subsystem stopped CORE0_STP_ACK 8 0 Core 0 Stop...

Page 296: ...31 8 0 Reserved Write to 0 for future compatibility LANE_D_XMIT_3S 7 1 Lane D Transmit Tristate Setting this bit forces the RapidIO lane D output to tristate 0 Normal output 1 Output tristated LANE_C_XMIT_3S 6 1 Lane C Transmit Tristate Setting this bit forces the RapidIO lane C output to tristate 0 Normal output 1 Output tristated LANE_B_XMIT_3S 5 1 Lane B Transmit Tristate Setting this bit force...

Page 297: ...he DDR_GCR bit field descriptions DDR_GCR DDR General Control Register Offset 0x10 Bit 31 30 29 28 27 26 25 24 Type R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Type R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDR_VSEL Type R W Reset 0 0 0 0 0 0 0 0 Table 8 5 DDR_GCR Bit Descriptions Name Reset Description Settings 31 1 0 Reserved...

Page 298: ..._XMIT_ EQ3 RIO_XMIT_EQ 2 0 RIO_RECV_ EQ3 RIO_RECV_EQ 1 0 Type R W Reset 0 0 1 1 0 0 0 1 Table 8 6 RIO_CR Bit Descriptions Name Reset Description Settings 31 10 0 Reserved Write to 0 for future compatibility RIO_EXTACCPL_EN 9 0 Proper External DC Coupling Enable Enables proper DC coupling when external coupling is used on RapidIO interface 0 Not enabled 1 Enabled RIO_INTACCPL_EN 8 1 Internal AC Amp...

Page 299: ...alization 01 2 dB of equalization 10 4 dB of equalization 11 Reserved SGMII_CR SGMII Control Register Offset 0x18 Bit 31 30 29 28 27 26 25 24 Type R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SGMII_ EXTACCPL_ EN SGMII_ INTACCPL_ EN Type R W Reset 0 0 0 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 SGMII_XMIT_EQ SGMII_RECV_EQ Type R W Reset 0 0 1 1 ...

Page 300: ...ister Offset 0x1C Bit 31 30 29 28 27 26 25 24 Type R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 UTP_RX_M UTP_TX_M Type R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 UTP_ENABLE ENET_SGMII _MODE1 ENET_SGMII _MODE0 Type R W Reset 0 0 0 0 0 0 0 0 Table 8 8 QECTLR Bit Descriptions Name Reset Description Settings 31 12 0 Reserved Write to...

Page 301: ...elects SGMII mode for Ethernet controller 1 0 SGMII1 not selected 1 SGMII1 selected 1 0 0 Reserved Write to 0 for future compatibility GIER GPIO Input Enable Register Offset 0x24 Bit 31 30 29 28 27 26 25 24 IE31 IE30 IE29 IE28 IE27 IE26 IE25 IE24 Type R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 IE23 IE22 IE21 IE20 IE19 IE18 IE17 IE16 Type R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9...

Page 302: ...28 Bit 31 30 29 28 27 26 25 24 PARTID Type R Reset 0 0 0 1 1 0 0 0 Bit 23 22 21 20 19 18 17 16 PARTID Type R Reset 0 0 0 0 0 1 1 1 Bit 15 14 13 12 11 10 9 8 REVID Type R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REVID Type R Reset 0 0 1 0 0 0 0 0 Table 8 10 SPRIDR Bit Descriptions for Mask Set M31H Name Reset Description Settings PARTID 31 16 0 Part Identification Mask programmed to indicate the d...

Page 303: ...e R W Reset 0 0 0 0 0 0 0 0 Table 8 11 GCR4 Bit Descriptions Name Reset Description Settings 31 20 0 Reserved Write to 0 for future compatibility UCC3RCLKID 19 18 0 UCC3 RX Clock In Delay Adds a delay to the specified signal 00 No delay 01 One delay unit 10 Two delay units 11 Three delay units UCC3TCLKID 17 16 0 UCC3 TX Clock In Delay Adds a delay to the specified signal 00 No delay 01 One delay u...

Page 304: ... 10 Two delay units 11 Three delay units UCC1RXDD 3 2 0 UCC1 RX Data Delay Adds a delay to the specified signal 00 No delay 01 One delay unit 10 Two delay units 11 Three delay units UCC1TXDD 1 0 0 UCC1 TX Data Delay Adds a delay to the specified signal 00 No delay 01 One delay unit 10 Two delay units 11 Three delay units GIR1 General Interrupt Register 1 Offset 0x40 Bit 31 30 29 28 27 26 25 24 Typ...

Page 305: ...d 0 Interrupt not asserted 1 Interrupt asserted VNMI_1 9 Virtual NMI 1 Asserted when VNMI_1 is activated 0 Interrupt not asserted 1 Interrupt asserted VNMI_0 8 Virtual NMI 0 Asserted when VNMI_0 is activated 0 Interrupt not asserted 1 Interrupt asserted 7 4 Reserved Write to zero for future compatibility M2_3_ECC 3 M2 Block 3 ECC Error Interrupt Asserted when ECC error is reported by M2_3 0 Interr...

Page 306: ...8 27 26 25 24 Type R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Type R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 M2_3_ECC_EN M2_2_ECC_EN M2_1_ECC_EN M2_0_ECC_EN Type R W Reset 0 0 0 0 0 0 0 0 Table 8 13 GIER1_n Bit Descriptions Name Description Settings 31 4 Reserved Write to zero for future compatibility M2_3_ECC_EN 3 M2 Block 3 ...

Page 307: ...riptions Name Description Settings 31 30 Reserved Write to zero for future compatibility SWT4 29 Software Watchdog Timer 4 Interrupt Reflects SWT 4 interrupt 0 Interrupt not asserted 1 Interrupt asserted SWT3 28 Software Watchdog Timer 3 Interrupt Reflects SWT 3 interrupt 0 Interrupt not asserted 1 Interrupt asserted SWT2 27 Software Watchdog Timer 2 Interrupt Reflects SWT 2 interrupt 0 Interrupt ...

Page 308: ...mit error interrupt 0 Interrupt not asserted 1 Interrupt asserted TDM5_RERR 10 TDM5 Receive Error Interrupt Reflects TDM5 Receive error interrupt 0 Interrupt not asserted 1 Interrupt asserted TDM4_TERR 9 TDM4 Transmit Error Interrupt Reflects TDM4 Transmit error interrupt 0 Interrupt not asserted 1 Interrupt asserted TDM4_RERR 8 TDM4 Receive Error Interrupt Reflects TDM4 Receive error interrupt 0 ...

Page 309: ...15 14 13 12 11 10 9 8 TDM7_TERR_EN TDM7_RERR_EN TDM6_TERR_EN TDM6_RERR_EN TDM5_TERR_EN TDM5_RERR_EN TDM4_TERR_EN TDM4_RERR_EN Type R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TDM3_TERR_EN TDM3_RERR_EN TDM2_TERR_EN TDM2_RERR_EN TDM1_TERR_EN TDM1_RERR_EN TDM0_TERR_EN TDM0_RERR_EN Type R W Reset 0 0 0 0 0 0 0 0 Table 8 15 GIER2_x Bit Descriptions Name Description Settings 31 30 Reserved Write to ze...

Page 310: ...rupt enabled TDM6_RERR_EN 12 TDM6 Receive Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM5_TERR_EN 11 TDM5 Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM5_RERR_EN 10 TDM5 Receive Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM4_TERR_EN 9 TDM4 Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM4_RERR_EN 8...

Page 311: ...it Descriptions Name Description Settings 31 12 Reserved Write to zero for future compatibility PM 11 Performance Monitor Interrupt Reflects the performance monitor interrupt 0 Interrupt not asserted 1 Interrupt asserted L2ICS_WP 10 L2 ICache Target CLASS Watchpoint Interrupt Reflects L2 ICache target CLASS watch point interrupt 0 Interrupt not asserted 1 Interrupt asserted L2ICS_OV 9 L2 ICache Ta...

Page 312: ...upt asserted CLS0_WP 1 CLASS0 Watchpoint Interrupt Reflects Class0 watchpoint interrupt 0 Interrupt not asserted 1 Interrupt asserted CLS0_OV 0 CLASS0 Overrun Interrupt Reflects CLASS0 overrun interrupt 0 Interrupt not asserted 1 Interrupt asserted GIER3_0 General Interrupt Enable Register 3 for Cores 0 3 Offset 0x6C GIER3_1 Offset 0x70 GIER3_2 Offset 0x74 GIER3_3 Offset 0x78 Bit 31 30 29 28 27 26...

Page 313: ...verrun Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled L2ICM_WP_EN 8 L2 ICache Initiator CLASS Watchpoint Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled L2ICM_OV_EN 7 L2 ICache Initiator CLASS Overrun Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled CLS2_WP_EN 6 CLASS2 Watchpoint Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled CLS2_OV_EN 5 CLASS2 Overrun Int...

Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...

Page 315: ...n interfaces of the SC3400 DSP core subsystem Note All addresses in this chapter are given as hexadecimal values 9 1 Shared Memory Address Space The shared memory address space resides within addresses 0x40000000 0xFEFFFFFF It includes the M2 memory M3 memory DDR memory PCI QUICC Engine subsystem and the boot ROM Table 9 1 Shared Memory Address Space Address Purpose Size in Bytes 40000000 5FFFFFFF...

Page 316: ...etails the QUICC Engine module address space Table 9 2 SC3400 DSP Core Subsystem Internal Address Space Address Purpose Size Bytes Remarks FF000000 FFEFFDFF Reserved 15 M 512 FFEFFE00 FFEFFFFF OCE 512 User Supervisor1 FFF000002 FFF003FF Reserved 1K FFF00400 FFF007FF EPIC 1K Supervisor FFF00800 FFF00BFF Data Cache registers 1K Supervisor FFF00C00 FFF00FFF Instruction Cache registers 1K Supervisor F...

Page 317: ...2 Bridge Register 512 0xFEE02C00 0xFEE02DFF reserved 512 0xFEE02E00 0xFEE02FFF MultiPHY Controller Registers 512 0xFEE03000 0xFEE03FFF reserved 4096 0xFEE04000 0xFEE0407F Serial DMA Registers 128 0xFEE04080 0xFEE040FF Debug Registers 128 0xFEE04100 0xFEE041FF RISC1 Special Registers trap and breakpoint 256 0xFEE04200 0xFEE042FF RISC1 Special Registers trap and breakpoint 256 0xFEE04300 0xFEE044FF ...

Page 318: ...271FF Hardware Semaphores 256 FFF27200 FFF272FF GPIO Registers 256 FFF27300 FFF29FFF Reserved 12 K 768 FFF2A000 FFF2AFFF L2 ICache Registers 4K FFF2B000 FFF2BFFF 4K FFF2C000 FFF2C01F 32 FFF2C020 FFF2FFFF Reserved 16 K 32 FFF30000 FFF33FFF TDM0 Registers 16 K FFF34000 FFF37FFF TDM1 Registers 16 K FFF38000 FFF3BFFF TDM2 Registers 16 K FFF3C000 FFF3FFFF TDM3 Registers 16 K FFF40000 FFF43FFF TDM4 Regi...

Page 319: ...pace as seen by the SC3400 data MBus interface FFF80000 FFF9FFFF RapidIO Registers 128 K FFFA0000 FFFA00FF OCN Crossbar Switch Registers 256 FFFA0100 FFFA0FFF Reserved 4 K 256 FFFA1000 FFFA103F OCN Crossbar Switch to MBus 64 FFFA1040 FFFA1FFF Reserved 4 K FFFA2000 FFFA3FFF Dedicated DMA Controller Registers 8 K FFFA4000 FFFC00FF Reserved 28 K 256 FFFC0100 FFFC01FF Performance Monitor Registers 256...

Page 320: ...FFFF Reserved 4 K Table 9 7 Peripherals View of the System Address Space Address Purpose Size Bytes 00000000 3FFFFFFF Reserved 1 G 40000000 FEFFFFFF Shared Memory Address Space 3 G 16 M FF000000 FFF0FFFF Reserved 15M 64K FFF10000 FFFFEFFF CCSR Address Space 956 K FFFFF000 FFFFFFFF Reserved 4 K Table 9 8 PCI View of the System Address Space Address Purpose Size Bytes 00000000 3FFFFFFF Reserved 1 G ...

Page 321: ...ss Space 956K FFFFF000 FFFFFFFF Reserved 4K Table 9 9 Consolidated Memory Map Address Name Status Acronym Reference 0x00000000 0x3FFFFFFF Reserved 0x40000000 0xFEFFFFFF Shared memory 0x40000000 0x5FFFFFFF DDR memory 0x60000000 0xBFFFFFFF reserved 0xC0000000 0xC007FFFF M2 Memory 0xC0080000 0xCFFFFFFF reserved 0xD0000000 0xD09FFFFF M3 Memory 0xD0A00000 0xDFFFFFFF reserved 0xE0000000 0xE7FFFFFF PCI A...

Page 322: ...k Register CIMR 0xFEE000A4 QUICC Engine RISC Interrupt Mask Register CRIMR 0xFEE000A8 QUICC Engine System Interrupt Control Register CICNR 0xFEE000AC 0xFEE000AF reserved 0xFEE000B0 QUICC Engine System Interrupt Priority Register for RISC Tasks A CIPRTA 0xFEE000B4 0xFEE000BB reserved 0xFEE000BC QUICC Engine System RISC Interrupt Control Register CRICR 0xFEE000C0 0xFEE000DF reserved 0xFEE000E0 QUICC...

Page 323: ... Rate Generator Configuration Register 7 BRGCR7 0xFEE0065C Baud Rate Generator Configuration Register 8 BRGCR8 0xFEE00660 0xFEE01FFF reserved 0xFEE02000 UCC 1 Mode Register GUMR1 0xFEE02004 UCC 1 Protocol Specific Mode Register UPSMR1 0xFEE02008 UCC 1 Transmit on Demand Register UTODR1 0xFEE0200A 0xFEE0200F reserved 0xFEE02010 UCC 1 Event Register UCCE1 0xFEE02014 UCC 1 Mask Register UCCM1 0xFEE02...

Page 324: ...II Management Command Register MIIMCOM1 0xFEE02128 Ethernet 1 MII Management Address Register MIIMADD1 0xFEE0212C Ethernet 1 MII Management Control Register MIIMCON1 0xFEE02130 Ethernet 1 MII Management Status Register MIIMSTAT1 0xFEE02134 Ethernet 1 MII Management Indication Register MIIMIND1 0xFEE0213C Ethernet 1 Interface Status Register IFSTAT1 0xFEE02140 Ethernet 1 Station Address Pt 1 Regist...

Page 325: ...GUMR3 0xFEE02204 UCC 3 Protocol Specific Mode Register UPSMR3 0xFEE02208 UCC 3 Transmit on Demand Register UTODR3 0xFEE0220A 0xFEE0220F reserved 0xFEE02210 UCC 3 Event Register UCCE3 0xFEE02214 UCC 3 Mask Registers UCCM3 0xFEE02218 UCC 3 Status Register UCCS3 0xFEE02219 0xFEE0221F reserved 0xFEE02220 UCC 3 Receive FIFO Base URFB3 0xFEE02224 UCC 3 Receive FIFO Size URFS3 0xFEE02226 0xFEE02227 reser...

Page 326: ...3 0xFEE0233C Ethernet 2 Interface Status Register IFSTAT3 0xFEE02340 Ethernet 2 Station Address Pt 1 Register E2MACSTNADDR1 0xFEE02344 Ethernet 2 Station Address Pt 2 Register E2MACSTNADDR2 0xFEE02348 0xFEE0234F reserved 0xFEE02350 Ethernet 2 Ethernet MAC Parameter Register UEMPR3 0xFEE02354 Ethernet 2 Ten Bit Interface Physical Address Register TBIPAR3 0xFEE02358 Ethernet 2 Ethernet Statistical C...

Page 327: ...EE02420 UCC 5 Receive l FIFO Base URFB5 0xFEE02424 UCC 5 Receive FIFO Size URFS5 0xFEE02426 0xFEE02427 reserved 0xFEE02428 UCC 5 Receive FIFO Emergency Threshold URFET5 0xFEE0242A UCC 5 Receive FIFO Special Emergency Threshold URFSET5 0xFEE0242C UCC 5 Transmit FIFO Base UTFB5 0xFEE02430 UCC 5 Transmit FIFO Size UTFS5 0xFEE02432 0xFEE02433 reserved 0xFEE02434 UCC 5 Transmit FIFO Emergency Threshold...

Page 328: ...IGSK SMII Receive Inter Frame Bits Register 2 MIIGSK2_RIFBR 0xFEE02A18 MIIGSK SMII Expected Receive Inter Frame Bits Register 2 MIIGSK2_ERIFBR 0xFEE02A1C MIIGSK Interrupt Event Register 2 MIIGSK2_IEVENT 0xFEE02A20 MIIGSK Interrupt Mask Register 2 MIIGSK2_IMASK 0xFEE02A24 0xFEE02DFF reserved 0xFEE02E00 UPC General Configuration Register UPGCR 0xFEE02E02 0xFEE02E03 reserved 0xFEE02E04 UPC Last PHY A...

Page 329: ...F reserved 0xFEE04010 Serial DMA Hysteresis Register SDHY 0xFEE04014 0xFEE04017 reserved 0xFEE04018 Serial DMA Address Register SDTA 0xFEE0401C 0xFEE0401F reserved 0xFEE04020 Serial DMA MSNUM Register SDTM 0xFEE04024 0xFEE04037 reserved 0xFEE04038 Serial DMA Address Qualify Register SDAQR 0xFEE0403C Serial DMA Address Qualify Mask Register SDAQMR 0xFEE04040 0xFEE04043 reserved 0xFEE04044 Serial DM...

Page 330: ...on Register LSBs ECFGL OCE RM 0xFFEFFE3C OCE Configuration Register MSBs ECFGH OCE RM 0xFFEFFE40 EDCA0 Control Register EDCA0_CTRL OCE RM 0xFFEFFE44 EDCA1 Control Register EDCA1_CTRL OCE RM 0xFFEFFE48 EDCA2 Control Register EDCA2_CTRL OCE RM 0xFFEFFE4C EDCA3 Control Register EDCA3_CTRL OCE RM 0xFFEFFE50 EDCA4 Control Register EDCA4_CTRL OCE RM 0xFFEFFE54 EDCA5 Control Register EDCA5_CTRL OCE RM 0x...

Page 331: ...FEFFED8 0xFFEFFEDF reserved 0xFFEFFEE0 EDCD Control Register EDCD_CTRL OCE RM 0xFFEFFEE4 EDCD Reference Register EDCD_REF OCE RM 0xFFEFFEE8 EDCD Mask Register EDCD_MASK OCE RM 0xFFEFFEEC 0xFFEFFEFF reserved 0xFFEFFF00 OCE Counter Control Register ECNT_CTRL OCE RM 0xFFEFFF04 OCE Counter Value ECNT_VAL OCE RM 0xFFEFFF08 OCE Extension Counter Value ECNT_EXT OCE RM 0xFFEFFF0C 0xFFEFFF1F reserved 0xFFE...

Page 332: ...ter 10 P_IPL10 0xFFF0042C EPIC Interrupt priority level Register 11 P_IPL11 0xFFF00430 EPIC Interrupt priority level Register 12 P_IPL12 0xFFF00434 EPIC Interrupt priority level Register 13 P_IPL13 0xFFF00438 EPIC Interrupt priority level Register 14 P_IPL14 0xFFF0043C EPIC Interrupt priority level Register 15 P_IPL15 0xFFF00440 EPIC Interrupt priority level Register 16 P_IPL16 0xFFF00444 EPIC Int...

Page 333: ...errupt priority level Register 43 P_IPL43 0xFFF004B0 EPIC Interrupt priority level Register 44 P_IPL44 0xFFF004B4 EPIC Interrupt priority level Register 45 P_IPL45 0xFFF004B8 EPIC Interrupt priority level Register 46 P_IPL46 0xFFF004BC EPIC Interrupt priority level Register 47 P_IPL47 0xFFF004C0 EPIC Interrupt priority level Register 48 P_IPL48 0xFFF004C4 EPIC Interrupt priority level Register 49 ...

Page 334: ... P_IPR7 0xFFF00540 EPIC Enable Disable interrupts register 0 P_ENDIS0 0xFFF00544 EPIC Enable Disable interrupts register 1 P_ENDIS1 0xFFF00548 EPIC Enable Disable interrupts register 2 P_ENDIS2 0xFFF0054C EPIC Enable Disable interrupts register 3 P_ENDIS3 0xFFF00550 EPIC Enable Disable interrupts register 4 P_ENDIS4 0xFFF00554 EPIC Enable Disable interrupts register 5 P_ENDIS5 0xFFF00558 EPIC Enab...

Page 335: ...system Reference Manual for details 0xFFF06000 MMU Control Register M_CR 0xFFF06004 MMU Data Status Register M_DSR 0xFFF06008 MMU Data Violation Access Register M_DVA 0xFFF0600C MMU Program Status Register M_PSR 0xFFF06010 MMU Program Violation Address Register M_PVA 0xFFF06014 0xFFF06027 reserved 0xFFF06028 MMU Platform Information Register M_PIR 0xFFF0602C 0xFFF0602F reserved 0xFFF06030 MMU Gene...

Page 336: ...Program Segment Descriptor Registers A4 M_PSDA4 0xFFF08044 MMU Program Segment Descriptor Registers B4 M_PSDB4 0xFFF08048 0xFFF0804F reserved 0xFFF08050 MMU Program Segment Descriptor Registers A5 M_PSDA5 0xFFF08054 MMU Program Segment Descriptor Registers B5 M_PSDB5 0xFFF08058 0xFFF0805F reserved 0xFFF08060 MMU Program Segment Descriptor Registers A6 M_PSDA6 0xFFF08064 MMU Program Segment Descrip...

Page 337: ...DA3 0xFFF09034 MMU Data Segment Descriptor Registers B3 M_DSDB3 0xFFF09038 0xFFF0903F reserved 0xFFF09040 MMU Data Segment Descriptor Registers A4 M_DSDA4 0xFFF09044 MMU Data Segment Descriptor Registers B4 M_DSDB4 0xFFF09048 0xFFF0904F reserved 0xFFF09050 MMU Data Segment Descriptor Registers A5 M_DSDA5 0xFFF09054 MMU Data Segment Descriptor Registers B5 M_DSDB5 0xFFF09058 0xFFF09FFF reserved 0xF...

Page 338: ...Address Register DP_TEA page 25 65 0xFFF0A088 DPU Trace Event Request Register DP_TER page 25 66 0xFFF0A08C DPU Trace Write Pointer Register DP_TW page 25 67 0xFFF0A090 DPU Trace Data Register DP_TD page 25 68 0xFFF0A094 0xFFF0A2FF reserved 0xFFF0A300 0xFFF0A3FF Core Timers See the MSC8144 SC3400 DSP Core Subsystem Reference Manual for details 0xFFF0A300 Timer 0 Control Register TM_T0C 0xFFF0A304 ...

Page 339: ...CR3 page 14 25 0xFFF10110 DMA Channel Configuration Register 4 DMACHCR4 page 14 25 0xFFF10114 DMA Channel Configuration Register 5 DMACHCR5 page 14 25 0xFFF10118 DMA Channel Configuration Register 6 DMACHCR6 page 14 25 0xFFF1011C DMA Channel Configuration Register 7 DMACHCR7 page 14 25 0xFFF10120 DMA Channel Configuration Register 8 DMACHCR8 page 14 25 0xFFF10124 DMA Channel Configuration Register...

Page 340: ...egister 13 DMAEDFTDL13 page 14 30 0xFFF1026C DMA Time To Deadline Register 14 DMAEDFTDL14 page 14 30 0xFFF10270 DMA Time To Deadline Register 15 DMAEDFTDL15 page 14 30 0xFFF10274 0xFFF10333 Reserved 0xFFF10334 DMA EDF Control Register DMAEDFCTRL page 14 31 0xFFF10338 DMA EDF Mask Register DMAEDFMR page 14 32 0xFFF1033C 0xFFF1033f Reserved 0xFFF10340 DMA EDF Mask Update Register DMAEDFMUR page 14 3...

Page 341: ...ng Register 4 C0PMR4 page 4 17 0xFFF18814 CLASS 0 Priority Mapping Register 5 C0PMR5 page 4 17 0xFFF18818 0xFFF1883F reserved 0xFFF18840 CLASS 0 Priority Auto Upgrade Value Register 0 C0PAVR0 page 4 19 0xFFF18844 CLASS 0 Priority Auto Upgrade Value Register 1 C0PAVR1 page 4 19 0xFFF18848 CLASS 0 Priority Auto Upgrade Value Register 2 C0PAVR2 page 4 19 0xFFF1884C CLASS 0 Priority Auto Upgrade Value...

Page 342: ... 4 26 0xFFF18A84 CLASS 0 Arbitration Weight Register 1 C0AWR1 page 4 26 0xFFF18A88 CLASS 0 Arbitration Weight Register 2 C0AWR2 page 4 26 0xFFF18A8C CLASS 0 Arbitration Weight Register 3 C0AWR3 page 4 26 0xFFF18A90 CLASS 0 Arbitration Weight Register 4 C0AWR4 page 4 26 0xFFF18A94 CLASS 0 Arbitration Weight Register 5 C0AWR5 page 4 26 0xFFF18A98 0xFFF18D7F reserved 0xFFF18D80 CLASS 0 IRQ Status Reg...

Page 343: ...ing Register 0 C1PMR0 page 4 17 0xFFF19804 CLASS 1 Priority Mapping Register 1 C1PMR1 page 4 17 0xFFF19808 CLASS 1 Priority Mapping Register 2 C1PMR2 page 4 17 0xFFF1980C CLASS 1 Priority Mapping Register 3 C1PMR3 page 4 17 0xFFF19810 CLASS 1 Priority Mapping Register 4 C1PMR4 page 4 17 0xFFF19814 CLASS 1 Priority Mapping Register 5 C1PMR5 page 4 17 0xFFF19818 0xFFF1983F reserved 0xFFF19840 CLASS ...

Page 344: ...guration Register 2 C1IPCR2 page 4 24 0xFFF19A0C CLASS 1 Initiator Profiling Configuration Register 3 C1IPCR3 page 4 24 0xFFF19A10 CLASS 1 Initiator Profiling Configuration Register 4 C1IPCR4 page 4 24 0xFFF19A14 CLASS 1 Initiator Profiling Configuration Register 5 C10IPCR5 page 4 24 0xFFF19A18 0xFFF19A3F reserved 0xFFF19A40 CLASS 1 Initiator Watch Point Control Register 0 C1IWPCR0 page 4 25 0xFFF...

Page 345: ... Point Extended Access Configuration Register C1WPEACR page 4 36 0xFFF19E14 CLASS 1 Watch Point Address Mask Register C1WPAMR page 4 38 0xFFF19E18 CLASS 1 Profiling Time Out Register C1PTOR page 4 39 0xFFF19E1C CLASS 1 Target Watch Point Control Register C1TWPCR page 4 40 0xFFF19E20 CLASS 1 Profiling IRQ Status Register C1PISR page 4 41 0xFFF19E24 CLASS 1 Profiling IRQ Enable Register C1PIER page ...

Page 346: ...nitiator Profiling Configuration Register 0 C2IPCR0 page 4 24 0xFFF1AA04 0xFFF1AA07 reserved 0xFFF1AA08 CLASS 2 Initiator Profiling Configuration Register 2 C2IPCR2 page 4 25 0xFFF1AA0C CLASS 2 Initiator Profiling Configuration Register 3 C2IPCR3 page 4 25 0xFFF1AA10 0xFFF1AA3F reserved 0xFFF1AA40 CLASS 2 Initiator Watch Point Control Register 0 C2IWPCR0 page 4 25 0xFFF1AA44 CLASS 2 Initiator Watc...

Page 347: ...E4C CLASS 2 Profiling General Counter Register 2 C2PGCR2 page 4 43 0xFFF1AE50 CLASS 2 Profiling General Counter Register 3 C2PGCR3 page 4 43 0xFFF1AE54 0xFFF1AF7F Reserved 0xFFF1AF80 CLASS 2 General Purpose Register C2GPR page 4 44 0xFFF1AF84 0xFFF1AFBF Reserved 0xFFF1AFC0 CLASS 2 Arbitration Control Register C2ACR page 4 45 0xFFF1AFC4 0xFFF1AFFF Reserved 0xFFF1B000 0xFFF1FFFF reserved 0xFFF20000 ...

Page 348: ...RR_INJECT_LO page 12 55 0xFFF20E08 Memory Data Path Error Injection Mask ECC DDR_ERR_INJECT page 12 55 0xFFF20E0C 0xFFF20E1F reserved 0xFFF20E20 Memory Data Path Read Capture High CAPTURE_DATA_HI page 12 56 0xFFF20E24 Memory Data Path Read Capture Low CAPTURE DATA_LO page 12 57 0xFFF20E28 Memory Data Path Read Capture ECC CAPTURE_ECC page 12 57 0xFFF20E2C 0xFFF20E3F reserved 0xFFF20E40 Memory Erro...

Page 349: ...ister1 DCMR1B page 7 22 0xFFF24048 0xFFF2404F reserved 0xFFF24050 Dividers Clock Mode Front Register0 DCMR0F page 7 20 0xFFF24054 Dividers Clock Mode Front Register1 DCMR1F page 7 22 0xFFF24058 0xFFF2405F reserved 0xFFF24060 PLL Auxiliary Mode Register0 PAMR0B page 7 23 0xFFF24064 PLL Auxiliary Mode Register1 PAMR1B page 7 24 0xFFF24068 PLL Auxiliary Mode Register2 PAMR2B page 7 24 0xFFF2406C 0xFF...

Page 350: ...gister I2CDFSRR page 24 20 0xFFF24C18 0xFFF24CFF reserved 0xFFF24D00 0xFFF24FFF reserved 0xFFF25000 0xFFF250FF Watchdog Timer 0 0xFFF25000 0xFFF25003 reserved 0xFFF25004 System Watchdog 0 Control Register SW0CRR page 21 25 0xFFF25008 System Watchdog 0 Count Register SW0CNR page 21 26 0xFFF2500C 0xFFF2500D reserved 0xFFF2500E System Watchdog 0 Service Register SW0SRR page 21 27 0xFFF25010 0xFFF250F...

Page 351: ...0xFFF25408 System Watchdog 4 Count Register SW4CNR page 21 26 0xFFF2540C 0xFFF2540D reserved 0xFFF2540E System Watchdog 4 Service Register SW4SRR page 21 27 0xFFF25410 0xFFF254FF reserved 0xFFF25500 0xFFF25FFF reserved 0xFFF26000 0xFFF260FF Timer 0 0xFFF26000 Timer 0 Channel 0 Compare 1 Register TMR0CMP10 page 21 21 0xFFF26004 Timer 0 Channel 0 Compare 2 Register TMR0CMP20 page 21 21 0xFFF26008 Ti...

Page 352: ...LOAD2 page 21 24 0xFFF26090 Timer 0 Channel 2 Hold Register TMR0HOLD2 page 21 24 0xFFF26094 Timer 0 Channel 2 Counter Register TMR0CNTR2 page 21 24 0xFFF26098 Timer 0 Channel 2 Control Register TMR0CTL2 page 21 17 0xFFF2609C Timer 0 Channel 2 Status and Control Register TMR0SCTL2 page 21 19 0xFFF260A0 Timer 0 Channel 2 Compare Load 1 Register TMR0CMPLD12 page 21 22 0xFFF260A4 Timer 0 Channel 2 Com...

Page 353: ...1 Counter Register TMR1CNTR1 page 21 24 0xFFF26158 Timer 1 Channel 1 Control Register TMR1CTL1 page 21 17 0xFFF2615C Timer 1 Channel 1 Status and Control Register TMR1SCTL1 page 21 19 0xFFF26160 Timer 1 Channel 1 Compare Load 1 Register TMR1CMPLD11 page 21 22 0xFFF26164 Timer 1 Channel 1 Compare Load 2 Register TMR1CMPLD21 page 21 22 0xFFF26168 Timer 1 Channel 1 Comparator Status and Control Regis...

Page 354: ... and Control Register TMR2SCTL0 page 21 19 0xFFF26220 Timer 2 Channel 0 Compare Load 1 Register TMR2CMPLD10 page 21 22 0xFFF26224 Timer 2 Channel 0 Compare Load 2 Register TMR2CMPLD20 page 21 22 0xFFF26228 Timer 2 Channel 0 Comparator Status and Control Register TMR2COMSC0 page 21 22 0xFFF2622C 0xFFF2623F reserved 0xFFF26240 Timer 2 Channel 1 Compare 1 Register TMR2CMP11 page 21 21 0xFFF26244 Time...

Page 355: ...3 Compare Load 2 Register TMR2CMPLD23 page 21 22 0xFFF262E8 Timer 2 Channel 3 Comparator Status and Control Register TMR2COMSC3 page 21 22 0xFFF262EC 0xFFF262FF reserved 0xFFF26300 0xFFF263FF Timer 3 0xFFF26300 Timer 3 Channel 0 Compare 1 Register TMR3CMP10 page 21 21 0xFFF26304 Timer 3 Channel 0 Compare 2 Register TMR3CMP20 page 21 21 0xFFF26308 Timer 3 Channel 0 Capture Register TMR3CAP0 page 21...

Page 356: ...r 3 Channel 2 Load 2 Register TMR3CMPLD22 page 21 22 0xFFF263A8 Timer 3 Channel 2 Comparator Status and Control Register TMR3COMSC2 page 21 22 0xFFF263AC 0xFFF263BF reserved 0xFFF263C0 Timer 3 Channel 3 Compare 1 Register TMR3CMP13 page 21 21 0xFFF263C4 Timer 3 Channel 3 Compare 2 Register TMR3CMP23 page 21 21 0xFFF263C8 Timer 3 Channel 3 Capture Register TMR3CAP3 page 21 23 0xFFF263CC Timer 3 Cha...

Page 357: ...page 23 2 0xFFF27124 0xFFF27127 reserved 0xFFF27128 Hardware Semaphore Register 5 HSMPR5 page 23 2 0xFFF2712C 0xFFF2712F reserved 0xFFF27130 Hardware Semaphore Register 6 HSMPR6 page 23 2 0xFFF27134 0xFFF27137 reserved 0xFFF27138 Hardware Semaphore Register 7 HSMPR7 page 23 2 0xFFF2713C 0xFFF271FF reserved 0xFFF27200 0xFFF272FF GPIO 0xFFF27200 Pin Open Drain Register PODR page 22 7 0xFFF27204 0xFF...

Page 358: ...C008 L2 ICache Control Register 2 L2IC_CR2 page 11 28 0xFFF2C00C L2 ICache LRM State Register L2IC_LRM page 11 29 0xFFF2C010 L2 ICache TAG State Register L2IC_TAG page 11 31 0xFFF2C014 L2 ICache Valid State Register L2IC_VALID page 11 32 0xFFF2C018 L2 ICache Data Register L2IC_DBG_DATA page 11 32 0xFFF2C01C L2 ICache Debug Access Register L2IC_DBG_ACS page 11 33 0xFFF2C020 0xFFF2FFFF reserved 0xFF...

Page 359: ...ster TDM0ASR page 19 71 0xFFF33F34 0xFFF33F37 reserved 0xFFF33F38 TDM0 Transmit Event Register TDM0TER page 19 70 0xFFF33F3C 0xFFF33F3F reserved 0xFFF33F40 TDM0 Receive Event Register TDM0RER page 19 69 0xFFF33F44 0xFFF33F47 reserved 0xFFF33F48 TDM0 Transmit Number of Buffers TDM0TNB page 19 69 0xFFF33F4C 0xFFF33F4F reserved 0xFFF33F50 TDM0 Receive Number of Buffers TDM0RNB page 19 68 0xFFF33F54 0...

Page 360: ...33FA7 reserved 0xFFF33FA8 TDM0 Receive Control Register TDM0RCR page 19 58 0xFFF33FAC 0xFFF33FAF reserved 0xFFF33FB0 TDM0 Adaptation Control Register TDM0ACR page 19 57 0xFFF33FB4 0xFFF33FB7 reserved 0xFFF33FB8 TDM0 Transmit Global Base Address TDM0TGBA page 19 55 0xFFF33FBC 0xFFF33FBF reserved 0xFFF33FC0 TDM0 Receive Global Base Address TDM0RGBA page 19 54 0xFFF33FC4 0xFFF33FC7 reserved 0xFFF33FC...

Page 361: ...xFFF36BFC TDM1 Transmit Channel Parameters Register 0 255 TDM1TCPR 0 255 page 19 63 0xFFF36C00 0xFFF37EFF reserved 0xFFF37F00 TDM1 Parity Control Register TDM1PCR page 19 57 0xFFF37F04 0xFFF37F07 reserved 0xFFF37F08 TDM1 Parity Error Register TDM1PER page 19 73 0xFFF37F0C 0xFFF37F0F reserved 0xFFF37F10 TDM1 Transmit Force Register TDM1TFR page 19 55 0xFFF37F14 0xFFF37F17 reserved 0xFFF37F18 TDM1 R...

Page 362: ...ved 0xFFF37F70 TDM1 Transmit Interrupt Enable Register TDM10TIER page 19 65 0xFFF37F74 0xFFF37F77 reserved 0xFFF37F78 TDM1 Receive Interrupt Enable Register TDM1RIER page 19 64 0xFFF37F7C 0xFFF37F7F reserved 0xFFF37F80 TDM1 Transmit Data Buffer Second Threshold TDM1TDBST page 19 61 0xFFF37F84 0xFFF37F87 reserved 0xFFF37F88 TDM1 Receive Data Buffer Second Threshold TDM1RDBST page 19 61 0xFFF37F8C 0...

Page 363: ... 19 48 0xFFF37FE4 0xFFF37FE7 reserved 0xFFF37FE8 TDM1 Transmit Interface Register TDM1TIR page 19 46 0xFFF37FEC 0xFFF37FEF reserved 0xFFF37FF0 TDM1 Receive Interface Register TDM1RIR page 19 44 0xFFF37FF4 0xFFF37FF7 reserved 0xFFF37FF8 TDM1 General Interface Register TDM1GIR page 19 36 0xFFF37FFC 0xFFF37FFF reserved 0xFFF38000 0xFFF3BFFF TDM2 0xFFF38000 0xFFF387FF TDM2 Receive Local Memory 0xFFF38...

Page 364: ...ansmit Event Register TDM2TER page 19 70 0xFFF3BF3C 0xFFF3BF3F reserved 0xFFF3BF40 TDM2 Receive Event Register TDM2RER page 19 69 0xFFF3BF44 0xFFF3BF47 reserved 0xFFF3BF48 TDM2 Transmit Number of Buffers TDM2TNB page 19 69 0xFFF3BF4C 0xFFF3BF4F reserved 0xFFF3BF50 TDM2 Receive Number of Buffers TDM2RNB page 19 68 0xFFF3BF54 0xFFF3BF57 reserved 0xFFF3BF58 TDM2 Transmit Data Buffer Displacement Regi...

Page 365: ... TDM2 Adaptation Control Register TDM2ACR page 19 57 0xFFF3BFB4 0xFFF3BFB7 reserved 0xFFF3BFB8 TDM2 Transmit Global Base Address TDM2TGBA page 19 55 0xFFF3BFBC 0xFFF3BFBF reserved 0xFFF3BFC0 TDM2 Receive Global Base Address TDM2RGBA page 19 54 0xFFF3BFC4 0xFFF3BFC7 reserved 0xFFF3BFC8 TDM2 Transmit Data Buffer Size TDM2TDBS page 19 54 0xFFF3BFCC 0xFFF3BFCF reserved 0xFFF3BFD0 TDM2 Receive Data Buf...

Page 366: ...ol Register TDM3PCR page 19 57 0xFFF3FFF04 0xFFF3FF07 reserved 0xFFF3FF08 TDM3 Parity Error Register TDM3PER page 19 73 0xFFF3FF0C 0xFFF3FF0F reserved 0xFFF3FF10 TDM3 Transmit Force Register TDM3TFR page 19 55 0xFFF3FF14 0xFFF3FF17 reserved 0xFFF3FF18 TDM3 Receive Force Register TDM3RFR page 19 56 0xFFF3FF1C 0xFFF3FF1F reserved 0xFFF3FF20 TDM3 Transmit Status Register TDM3TSR page 19 73 0xFFF3FF24...

Page 367: ...78 TDM3 Receive Interrupt Enable Register TDM3RIER page 19 64 0xFFF3FF7C 0xFFF3FF7F reserved 0xFFF3FF80 TDM3 Transmit Data Buffer Second Threshold TDM3TDBST page 19 61 0xFFF3FF84 0xFFF3FF87 reserved 0xFFF3FF88 TDM3 Receive Data Buffer Second Threshold TDM3RDBST page 19 61 0xFFF3FF8C 0xFFF3FF8F reserved 0xFFF3FF90 TDM3 Transmit Data Buffer First Threshold TDM3TDBFT page 19 60 0xFFF3FF94 0xFFF3FF97 ...

Page 368: ...6 0xFFF3FFEC 0xFFF3FFEF reserved 0xFFF3FFF0 TDM3 Receive Interface Register TDM3RIR page 19 44 0xFFF3FFF4 0xFFF3FFF7 reserved 0xFFF3FFF8 TDM3 General Interface Register TDM3GIR page 19 36 0xFFF3FFFC 0xFFF3FFFF reserved 0xFFF40000 0xFFF43FFF TDM4 0xFFF40000 0xFFF407FF TDM4 Receive Local Memory 0xFFF40800 0xFFF40FFF reserved 0xFFF41000 0xFFF413FC TDM4 Receive Channel Parameters Register 0 255 TDM4RC...

Page 369: ...eive Event Register TDM4RER page 19 69 0xFFF43F44 0xFFF43F47 reserved 0xFFF43F48 TDM4 Transmit Number of Buffers TDM4TNB page 19 69 0xFFF43F4C 0xFFF43F4F reserved 0xFFF43F50 TDM4 Receive Number of Buffers TDM4RNB page 19 68 0xFFF43F54 0xFFF43F57 reserved 0xFFF43F58 TDM4 Transmit Data Buffer Displacement Register TDM4TDBDR page 19 67 0xFFF43F5C 0xFFF43F5F reserved 0xFFF43F60 TDM4 Receive Data Buffe...

Page 370: ...ed 0xFFF43FB8 TDM4 Transmit Global Base Address TDM4TGBA page 19 55 0xFFF43FBC 0xFFF43FBF reserved 0xFFF43FC0 TDM4 Receive Global Base Address TDM4RGBA page 19 54 0xFFF43FC4 0xFFF43FC7 reserved 0xFFF43FC8 TDM4 Transmit Data Buffer Size TDM4TDBS page 19 54 0xFFF43FCC 0xFFF43FCF reserved 0xFFF43FD0 TDM4 Receive Data Buffer Size TDM4RDBS page 19 53 0xFFF43FD4 0xFFF43FD7 reserved 0xFFF43FD8 TDM4 Trans...

Page 371: ...04 0xFFF47F07 reserved 0xFFF47F08 TDM5 Parity Error Register TDM5PER page 19 73 0xFFF47F0C 0xFFF47F0F reserved 0xFFF47F10 TDM5 Transmit Force Register TDM5TFR page 19 55 0xFFF47F14 0xFFF47F17 reserved 0xFFF47F18 TDM5 Receive Force Register TDM5RFR page 19 56 0xFFF47F1C 0xFFF47F1F reserved 0xFFF47F20 TDM5 Transmit Status Register TDM5TSR page 19 73 0xFFF47F24 0xFFF47F27 reserved 0xFFF47F28 TDM5 Rec...

Page 372: ...7C 0xFFF47F7F reserved 0xFFF47F80 TDM5 Transmit Data Buffer Second Threshold TDM5TDBST page 19 61 0xFFF47F84 0xFFF47F87 reserved 0xFFF47F88 TDM5 Receive Data Buffer Second Threshold TDM5RDBST page 19 61 0xFFF47F8C 0xFFF47F8F reserved 0xFFF47F90 TDM5 Transmit Data Buffer First Threshold TDM5TDBFT page 19 60 0xFFF47F94 0xFFF47F97 reserved 0xFFF47F98 TDM5 Receive Data Buffer First Threshold TDM5RDBFT...

Page 373: ...age 19 44 0xFFF47FF4 0xFFF47FF7 reserved 0xFFF47FF8 TDM5 General Interface Register TDM5GIR page 19 36 0xFFF47FFC 0xFFF47FFF reserved 0xFFF48000 0xFFF4BFFF TDM6 0xFFF48000 0xFFF487FF TDM6 Receive Local Memory 0xFFF48800 0xFFF48FFF reserved 0xFFF49000 0xFFF493FC TDM6 Receive Channel Parameters Register 0 255 TDM6RCPR 0 255 page 19 62 0xFFF49400 0xFFF497FF reserved 0xFFF49800 0xFFF49FFF TDM6 Transmi...

Page 374: ...f Buffers TDM6TNB page 19 69 0xFFF4BF4C 0xFFF4BF4F reserved 0xFFF4BF50 TDM6 Receive Number of Buffers TDM6RNB page 19 68 0xFFF4BF54 0xFFF4BF57 reserved 0xFFF4BF58 TDM6 Transmit Data Buffer Displacement Register TDM6TDBDR page 19 67 0xFFF4BF5C 0xFFF4BF5F reserved 0xFFF4BF60 TDM6 Receive Data Buffer Displacement Register TDM6RDBDR page 19 67 0xFFF4BF64 0xFFF4BF67 reserved 0xFFF4BF68 TDM6 Adaptation ...

Page 375: ...FBC 0xFFF4BFBF reserved 0xFFF4BFC0 TDM6 Receive Global Base Address TDM6RGBA page 19 54 0xFFF4BFC4 0xFFF4BFC7 reserved 0xFFF4BFC8 TDM6 Transmit Data Buffer Size TDM6TDBS page 19 54 0xFFF4BFCC 0xFFF4BFCF reserved 0xFFF4BFD0 TDM6 Receive Data Buffer Size TDM6RDBS page 19 53 0xFFF4BFD4 0xFFF4BFD7 reserved 0xFFF4BFD8 TDM6 Transmit Frame Parameters TDM6TFP page 19 51 0xFFF4BFDC 0xFFF4BFDF reserved 0xFF...

Page 376: ...FFF4FF0C 0xFFF4FF0F reserved 0xFFF4FF10 TDM7 Transmit Force Register TDM7TFR page 19 55 0xFFF4FF14 0xFFF4FF17 reserved 0xFFF4FF18 TDM7 Receive Force Register TDM7RFR page 19 56 0xFFF4FF1C 0xFFF4FF1F reserved 0xFFF4FF20 TDM7 Transmit Status Register TDM7TSR page 19 73 0xFFF4FF24 0xFFF4FF27 reserved 0xFFF4FF28 TDM7 Receive Status Register TDM7RSR page 19 72 0xFFF4FF2C 0xFFF4FF2F reserved 0xFFF4FF30 ...

Page 377: ... page 19 61 0xFFF4FF84 0xFFF4FF87 reserved 0xFFF4FF88 TDM7 Receive Data Buffer Second Threshold TDM7RDBST page 19 61 0xFFF4FF8C 0xFFF4FF8F reserved 0xFFF4FF90 TDM7 Transmit Data Buffer First Threshold TDM7TDBFT page 19 60 0xFFF4FF94 0xFFF4FF97 reserved 0xFFF4FF98 TDM7 Receive Data Buffer First Threshold TDM7RDBFT page 19 59 0xFFF4FF9C 0xFFF4FF9F reserved 0xFFF4FFA0 TDM7 Transmit Control Register T...

Page 378: ...FFF78008 General Status Register 1 GSR1 page 8 4 0xFFF7800C Lynx General Configuration Register L_GCR page 8 6 0xFFF78010 DDR General Control Register DDR_GCR page 8 7 0xFFF78014 RapidIO Control Register RIO_CR page 8 8 0xFFF78018 SGMII Control Register SGMII_CR page 8 9 0xFFF7801C QUICC Engine Control Register CECTLR page 8 10 0xFFF78020 reserved 0xFFF78024 GPIO Input Enable Register GIER page 8 ...

Page 379: ...xFFF7A010 PCI Error Address Capture Register PCI_EACR page 15 39 0xFFF7A014 PCI Error Extended Address Capture Register PCI_EEACR page 15 39 0xFFF7A018 PCI Error Data Low Capture Register PCI_EDCR page 15 40 0xFFF7A020 0xFFF7A037 reserved 0xFFF7A038 PCI Inbound Translation Address Register 2 PITAR2 page 15 40 0xFFF7A03C 0xFFF7A03F reserved 0xFFF7A040 PCI Inbound Base Address Register 2 PIBAR2 page...

Page 380: ... Base Address Register 2 POBAR2 page 15 44 0xFFF7A13C 0xFFF7A13F reserved 0xFFF7A140 PCI Outbound Comparison Mask Register 2 POCMR2 page 15 44 0xFFF7A144 0xFFF7A147 reserved 0xFFF7A148 PCI Outbound Translation Address Register 3 POTAR3 page 15 43 0xFFF7A14C 0xFFF7A14F reserved 0xFFF7A150 PCI Outbound Base Address Register 3 POBAR3 page 15 44 0xFFF7A154 0xFFF7A157 reserved 0xFFF7A158 PCI Outbound C...

Page 381: ...page 20 31 0xFFF7F01C 0xFFF7F027 reserved 0xFFF7F028 SCI Data Direction Register SCIDDR page 20 32 0xFFF7F02C 0xFFF7F03F reserved 0xFFF7F040 0xFFF7FFFF reserved 0xFFF80000 0xFFF9FFFF RapidIO 0xFFF80000 Device Identity Capability Register DIDCAR page 16 104 0xFFF80004 Device Information Capability Register DICAR page 16 105 0xFFF80008 Assembly Identity Capability Register AIDCAR page 16 105 0xFFF80...

Page 382: ...tus Register PRTOCCSR page 16 121 0xFFF80128 0xFFF8013B reserved 0xFFF8013C Port General Control Command and Status Register PGCCSR page 16 122 0xFFF80140 0xFFF80147 reserved 0xFFF80148 Port 0 Local ackID Status Command and Status Register P0LASCSR page 16 125 0xFFF8014C 0xFFF80157 reserved 0xFFF80158 Error and Status Command and Status Register ESCSR page 16 126 0xFFF8015C Port 0 Control Command ...

Page 383: ... page 16 144 0xFFF8066C Port 0 Error Rate Threshold Command and Status Register P0ERTCSR page 16 145 0xFFF80670 0xFFF90003 reserved 0xFFF90004 Logical Layer Configuration Register LLCR page 16 146 0xFFF90008 0xFFF9000F reserved 0xFFF90010 Error Port Write Interrupt Status Register EPWISR page 16 147 0xFFF90014 0xFFF9001F reserved 0xFFF90020 Logical Retry Error Threshold Configuration Register LRET...

Page 384: ...OWTAR1 page 16 158 0xFFF90C24 Port 0 RapidIO Outbound Window Translation Extended Address Register 1 P0ROWTEAR1 page 16 159 0xFFF90C28 Port 0 RapidIO Outbound Window Base Address Register 1 P0ROWBAR1 page 16 162 0xFFF90C2C 0xFFF90C2F reserved 0xFFF90C30 Port 0 RapidIO Outbound Window Attributes Register 1 P0ROWAR1 page 16 160 0xFFF90C34 0xFFF90C3F reserved 0xFFF90C40 Port 0 RapidIO Outbound Window...

Page 385: ...CAF reserved 0xFFF90CB0 Port 0 RapidIO Outbound Window Attributes Register 5 P0ROWAR5 page 16 160 0xFFF90CB4 0xFFF90CBF reserved 0xFFF90CC0 Port 0 RapidIO Outbound Window Translation Address Register 6 P0ROWTAR6 page 16 158 0xFFF90CC4 Port 0 RapidIO Outbound Window Translation Extended Address Register 6 P0ROWTEAR6 page 16 159 0xFFF90CC8 Port 0 RapidIO Outbound Window Base Address Register 6 P0ROW...

Page 386: ...reserved 0xFFF90D88 RapidIO Inbound Window Base Address Register 3 RIWBAR3 page 16 165 0xFFF90D8C 0xFFF90D8F reserved 0xFFF90D90 RapidIO Inbound Window Attributes Register 3 RIWAR3 page 16 166 0xFFF90D94 0xFFF90D9F reserved 0xFFF90DA0 RapidIO Inbound Window Translation Address Register 2 RIWTAR2 page 16 164 0xFFF90DA4 0xFFF90DA7 reserved 0xFFF90DA8 RapidIO Inbound Window Base Address Register 2 RI...

Page 387: ...criptor Queue Enqueue Pointer Address Register OM0DQEPAR page 16 176 0xFFF9302C Outbound Message 0 Retry Error Threshold Configuration Register OM0RETCR page 16 177 0xFFF93030 Outbound Message 0 Multicast Group Register OM0MGR page 16 178 0xFFF93034 Outbound Message 0 Multicast List Register OM0MLR page 16 179 0xFFF93038 0xFFF9305F reserved 0xFFF93060 Inbound Message 0 Mode Register IM0MR page 16 ...

Page 388: ...age 1 Mode Register IM1MR page 16 180 0xFFF93164 Inbound Message 1 Status Register IM1SR page 16 182 0xFFF93168 0xFFF9316B reserved 0xFFF9316C Inbound Message 1 Frame Queue Dequeue Pointer Address Register IM1FQDPAR page 16 184 0xFFF93170 0xFFF93173 reserved 0xFFF93174 Inbound Message 1 Frame Queue Enqueue Pointer Address Register IM1FQEPAR page 16 185 0xFFF93178 Inbound Message 1 Maximum Interrup...

Page 389: ... 0xFFFA2000 0xFFFA3FFF Dedicated DMA Controller for RapidIO Interface Registers 0xFFFA2000 0xFFFA20FF reserved 0xFFFA2100 DMA 0 Mode Register MR0 0xFFFA2104 DMA 0 Status Register SR0 0xFFFA2108 DMA 0 Current Link Descriptor Extended Address Register ECLNDAR0 0xFFFA210C DMA 0 Current Link Descriptor Address Register CLNDAR0 0xFFFA2110 DMA 0 Source Attributes Register SATR0 0xFFFA2114 DMA 0 Source A...

Page 390: ...B8 DMA 1 Next List Descriptor Extended Address Register ENLSDAR1 0xFFFA21BC DMA 1 Next List Descriptor Address Register NLSDAR1 0xFFFA21C0 DMA 1 Source Stride Register SSR1 0xFFFA21C4 DMA 1 Destination Stride Register DSR1 0xFFFA21C8 0xFFFA21FF reserved 0xFFFA2200 DMA 2 Mode Register MR2 0xFFFA2204 DMA 2 Status Register SR2 0xFFFA2208 DMA 2 Current Link Descriptor Extended Address Register ECLNDAR...

Page 391: ...t List Descriptor Extended Address Register ECLSDAR3 0xFFFA22B4 DMA 3 Current List Descriptor Address Register CLSDAR3 0xFFFA22B8 DMA 3 Next List Descriptor Extended Address Register ENLSDAR3 0xFFFA22BC DMA 3 Next List Descriptor Address Register NLSDAR3 0xFFFA22C0 DMA 3 Source Stride Register SSR3 0xFFFA22C4 DMA 3 Destination Stride Register DSR3 0xFFFA22C8 0xFFFA22FF reserved 0xFFFA2300 DMA Gene...

Page 392: ...ved 0xFFFA3CC8 Local Access Window Base Address Register 6 LAWBAR6 0xFFFA3CCC 0xFFFA3CCF reserved 0xFFFA3CD0 Local Access Window Attributes Register 6 LAWAR6 0xFFFA3CD4 0xFFFA3CE7 reserved 0xFFFA3CE8 Local Access Window Base Address Register 7 LAWBAR7 0xFFFA3CEC 0xFFFA3CEF reserved 0xFFFA3CF0 Local Access Window Attributes Register 7 LAWAR7 0xFFFA3CF4 0xFFFA3D07 reserved 0xFFFA3D08 Local Access Wi...

Page 393: ...gister A3 PMLCA3 page 25 81 0xFFFC0144 Performance Monitor Local Control Register B3 PMLCB3 page 25 83 0xFFFC0148 Performance Monitor Counter 3 PMC3 page 25 85 0xFFFC014C 0xFFFC014F reserved 0xFFFC0150 Performance Monitor Local Control Register A4 PMLCA4 page 25 81 0xFFFC0154 Performance Monitor Local Control Register B4 PMLCB4 page 25 83 0xFFFC0158 Performance Monitor Counter 4 PMC4 page 25 85 0x...

Page 394: ...trol Register MCR page 26 77 0xFFFD1038 0xFFFD1107 reserved 0xFFFD1108 Channel 1 Configuration Register CCR1 page 26 89 0xFFFD1110 Channel 1 Pointer Status Register CPSR1 page 26 92 0xFFFD1118 0xFFFD113F reserved 0xFFFD1140 Channel 1 Current Descriptor Pointer Register CDPR1 page 26 98 0xFFFD1148 Channel 1 Fetch FIFO CFF1 page 26 99 0xFFFD1150 0xFFFD117F reserved 0xFFFD1180 0xFFFD11BF Channel 1 De...

Page 395: ...D13E0 0xFFFD13FF Channel 3 Scatter Link Tables page 26 76 0xFFFD1400 0xFFFD1407 reserved 0xFFFD1408 Channel 4 Configuration Register CCR4 page 26 89 0xFFFD1410 Channel 4 Pointer Status Register CPSR4 page 26 92 0xFFFD1418 0xFFFD143F reserved 0xFFFD1440 Channel 4 Current Descriptor Pointer Register CDPR4 page 26 98 0xFFFD1448 Channel 4 Fetch FIFO CFF4 page 26 99 0xFFFD1450 0xFFFD147F reserved 0xFFF...

Page 396: ...000 AESU Mode Register AESUMR page 26 124 0xFFFD4008 AESU Key Size Register AESUKSR page 26 126 0xFFFD4010 AESU Data Size Register AESUDSR page 26 127 0xFFFD4018 AESU Reset Control Register AESURCR page 26 128 0xFFFD4020 0xFFFD4027 reserved 0xFFFD4028 AESU Status Register AESUSR page 26 129 0xFFFD4030 AESU Interrupt Status Register AESUISR page 26 130 0xFFFD4038 AESU Interrupt Mask Register AESUIM...

Page 397: ... Register MDEUISR page 26 142 0xFFFD6038 MDEU Interrupt Mask Register MDEUIMR page 26 144 0xFFFD6040 MDEU ICV Size Register MDEUICVSR page 26 146 0xFFFD6048 0xFFFD604F reserved 0xFFFD6050 MDEU End_of_Message Register MDEUEOMR page 26 147 0xFFFD6058 0xFFFD60FF reserved 0xFFFD6100 0xFFFD6120 MDEU Context Registers MDEUCR page 26 147 0xFFFD6128 0xFFFD63FF reserved 0xFFFD6400 0xFFFD647F MDEU Key Regis...

Page 398: ...gh the input FIFO page 26 160 0xFFFD9000 0xFFFD9FFF reserved 0xFFFDA000 RNG Mode Register RNGMR page 26 179 0xFFFDA008 0xFFFDA00F reserved 0xFFFDA010 RNG Data Size Register RNGDSR page 26 180 0xFFFDA018 RNG Reset Control Register RNGRCR page 26 181 0xFFFDA020 0xFFFDA027 reserved 0xFFFDA028 RNG Status Register RNGSR page 26 182 0xFFFDA030 RNG Interrupt Status Register RNGISR page 26 183 0xFFFDA038 ...

Page 399: ...FFDC33F PKEU Parameter Memory B0 page 26 111 0xFFFDC340 0xFFFDC37F PKEU Parameter Memory B1 page 26 111 0xFFFDC380 0xFFFDC3BF PKEU Parameter Memory B2 page 26 111 0xFFFDC3C0 0xFFFDC3FF PKEU Parameter Memory B3 page 26 111 0xFFFDC400 0xFFFDC4FF PKEU Parameter Memory E page 26 111 0xFFFDC500 0xFFFDC7FF reserved 0xFFFDC800 0xFFFDC8FF PKEU Parameter Memory N page 26 111 0xFFFDC900 0xFFFDDFFF reserved ...

Page 400: ... Context Register 3 KEUCR3 page 26 176 0xFFFDE130 KEU Context Register 4 KEUCR4 page 26 176 0xFFFDE138 KEU Context Register 5 KEUCR5 page 26 176 0xFFFDE140 KEU Context Register 6 KEUCR6 page 26 176 0xFFFDE148 0xFFFDE3FF reserved 0xFFFDE400 KEU Key Data Register 1 KEUKDR1 page 26 177 0xFFFDE408 KEU Key Data Register 2 KEUKDR2 page 26 177 0xFFFDE410 KEU Key Data Register 3 KEUKDR3 page 26 178 0xFFFD...

Page 401: ...ess port TAP on chip emulator OCE and debug and profiling unit DPU Dual timer Two interfaces instruction and data to link the QBus structure supported by the SC3400 core with the MBus used to interface with the other functional blocks in the MSC8144 device Five operating states including two core power saving modes Note The SC3400 DSP Core Reference Manual and the MSC8144 SC3400 DSP Core Subsystem...

Page 402: ...y combination For example the core can execute four multiply accumulate operations in a single clock or one MAC two arithmetic logical operations and one bit field operation All four data ALUs are identical This permits great flexibility in the assignment and execution of instructions increasing the likelihood that four execution units can be kept busy on any given cycle and enabling programs to t...

Page 403: ...bility and so forth The MMU performs address translation on external to the DSP core subsystem addresses from virtual addresses used by the software that runs on the core to physical addresses used by the MBuses Address translation is needed for several reasons including Enabling the software to be written without consideration of the physical location of the code in memory thereby providing a sim...

Page 404: ...nel The Instruction Channel comprises the Instruction Cache ICache and the Instruction Fetch Unit IFU This channel provides the core with instructions that are stored in higher level memory The ICache which operates at core speed stores recently accessed instructions Whenever an addressed instruction from the cacheable memory area is found in the array it is immediately made available to the core ...

Page 405: ...FU and driven to the core The DFU operates in parallel with the core and implements a pre fetch algorithm to load to the DCache Because there is a high probability that the information will be needed again the loading of the data can reduce the number of data cache misses The channel differentiates between cacheable and non cacheable addresses For cacheable addresses it supports the write back all...

Page 406: ...his includes interrupts generated by the MSC8144E internal peripherals and external interrupt input lines The role of the EPIC module is to manage the interrupt inputs The EPIC manages the interrupts using a fixed set of priority rules and passes interrupts with the highest priority at any given time to the core The EPIC also manages the acknowledgment of edge triggered interrupts The EPIC handles...

Page 407: ...ng behavior of the application during this process The DPU has three major debug and profiling functions Counting system events Managing the Virtual Trace Buffer VTB Generating data The DPU has the following characteristics Enables parallel counting of platform events in 6 dedicated counters from more than 40 events Filter process and add task ID and profiling information on the OCE PC trace infor...

Page 408: ... domains internal and external The two clock domains are asynchronous The internal clock domain runs at the core frequency and the external clock is slower to comply with the other block requirements The interfaces include the following Bus widths 128 bit data buses read write for both buses 32 bit address bus for both buses 8 bit line byte count Frequency reduction from the QBus frequency and the...

Page 409: ...CE register RD_STATUS In this state a debugging agent external to the DSP core subsystem can access various internal platform registers and memory locations in order to develop and debug the application that is intended to run on the architecture See the SC3000 Core Reference Manual for details about Debug state The platform enters Debug state after one of the following occurs Assertion of dedicat...

Page 410: ...acknowledge signal protocol is initiated between the blocks of DSP core subsystem and the external environment in order to ensure that the platform is idle and for the external environment to acknowledge that the platform can enter STOP state The platform exits STOP state when a dedicated input is asserted from outside the platform or when the platform is transferred to Debug state or to Reset sta...

Page 411: ...core subsystem For example the SC3400 core samples a dedicated input bus to determine the reset vector first address during the reset signal deassertion Note The SC3400 performs the transition from the Reset state to the Execution state and Exception working mode Please refer to the SC3000 Core Reference Manual for details on this transition 10 9 6 2 Transition from Reset to Debug State This trans...

Page 412: ...tion to WAIT State The DSP core subsystem can switch to the WAIT state only in one of the non protected working modes Execution or Normal of the Execution state The transition is done by executing the WAIT instruction by the SC3400 core 10 9 6 7 Transition from STOP WAIT to Debug state This transition is initiated in one of the following conditions The JTAG DEBUG REQUEST instruction is requested b...

Page 413: ... 6 9 Transition from WAIT to Execution state The transition from the WAIT state is done by the assertion of one of the following exit from WAIT signals An interrupt request that is enabled by the core is asserted A non maskable interrupt NMI request is issued The JTAG DEBUG REQUEST command is issued to the external JTAG controller requires that the OCE is pre programmed as described in the note be...

Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...

Page 415: ...le from all DSP subsystems and all CLASS initiators via four interleaved ports 10 MB 128 bit wide M3 memory accessed at up to 400 MHz Accessible from all DSP subsystems and all CLASS initiators Most applications run with no external memory 96 KB of boot ROM accessible from the cores Note The MMU L1 ICache and L1 DCache are part of the MSC8144 SC3400 DSP core subsystem For detailed programming and ...

Page 416: ...ole for the OCE and internal device registers and peripherals The core generates virtual addresses during its operation The virtual address together with the task ID from the MMU become the task extended TE virtual address The MMU translates between virtual and physical addresses during each core access providing control attributes for each core access per memory segment such as burst size pre fet...

Page 417: ...or each data program memory region enables allocating virtual memory region to a valid physical memory space Priority mechanism between descriptors allowing memory regions overlapping Stores the program task ID and data task ID for multi task mechanism Up to 255 different Program IDs and 255 different data IDs are available General Purpose registers among its control and status registers Access er...

Page 418: ...rom the MMU is stored as part of the line tag that allows a task specific cache image that is not overridden by other tasks that use the same virtual address This feature can support multi task mechanism This extended tag is named the ETAG Cacheable shared memory between tasks marked by the MMU according to the memory range and stored in the cache with TASKID 0 Cache hit access without wait states...

Page 419: ...rammable cache control registers that control or reflect its operation EDC error detection support Dedicated exceptions for each of the following events End of sweep operation This exception indicates the completion of the sweep operation XP non cacheable hit access This exception indicates that an access is a hit access even though the MMU classifies it as a non cacheable access This type of situ...

Page 420: ...ently as identified in the MMU based on their address ranges Task extended virtually addressed cache The 8 bit task ID from the MMU is stored as part of the line tag which allows a task specific cache image that is not overridden by other tasks that use the same virtual address This feature can support multi task mechanism This extended tag is named ETAG in this chapter Supports cacheable shared m...

Page 421: ... dirty bit and also invalidate it in the cache clearing the valid bit Invalidate discard the cache line without writing it back clear both dirty and valid bits Cache debug mode where the cache state ETAG values Valid Dirty PLRU state could be read and the memory array could be read or written to Dedicated programmable cache control registers that control or reflect its operation EDC error detectio...

Page 422: ...mand in the same way as in the SC3400 L1 ICache which is useful when new code is written to M2 M3 or DDR memory that is already cached All DSP subsystem instruction addresses are interleaved to two L2 ICache ports so they can service multiple requesters concurrently if they access different interleaved banks Figure 11 1 shows the L2 ICache block diagram The two memory banks Bank 1 and Bank 2 both ...

Page 423: ...6 byte cache line size 16 VBRs 8 32 256 cache lines TAGs per bank L2 ICache initiator and target buses are 128 bits wide The L2 ICache connects to four initiators the 4 cores and one target the internal MBus Supports both cacheable and non cacheable accesses determined by a user configured address range Supports wrap transactions Supports big endian data Cache contains dedicated registers for prog...

Page 424: ...After interleaving the lsb of the 6 bit index is removed and each bank uses a 5 bit index as shown in Figure 11 2 Each cache way includes 32 cache lines 5 bit index after the 6 bit index is used to interleave between the banks Each line includes 256 bytes of data 16 bytes in each VBR To locate the instruction cache line that matches the access the tag is compared to those which are stored in the c...

Page 425: ...e memory that serves cores hit accesses and to which data is fetched due to miss accesses The memory unit inside each module is four single precompiled memories of 2048 72 bit words 11 4 3 Instruction Fetch Unit The instruction fetch unit is active only for L2 ICache cacheable accesses It requests fetch sets from devices connected to the MBus and drives that data to the L2 ICache memory Figure 11 ...

Page 426: ... cache policies 11 4 6 Functional Mode of Operation This is the normal processing state in which each DSP core subsystem freely executes instructions and initiates memory accesses 11 4 6 1 Enabling the L2 ICache The CLASS does not return request acknowledge signals during reset Therefore the L2 ICache cannot respond to core requests during reset After reset the L2 ICache is in non cacheable mode o...

Page 427: ...locked new data fetches are not written to the L2 ICache and no lines are trashed Hit accesses are served as usual Miss accesses are served without updating the cache memory The PLRU machine is not updated while the L2 ICache is locked The L2 ICache Global Lock mode may be useful to improve the performance of some applications that may be sensitive to interrupts for example After asserting this mo...

Page 428: ...decision tree PLRU algorithm There is an identifying bit for each cache way L 0 7 There are seven PLRU bits B 0 6 for each index in the cache to determine the line to be replaced The PLRU bits are updated when a new line is allocated or replaced and when there is a line hit A line is selected for replacement according to the PLRU bit encoding shown in Table 11 1 initial values of B 6 0 is all zero...

Page 429: ...inverse operation all the PLRU status bit change their state causing the allocation sequence to be inverted 11 4 6 6 L2 ICache Sweep Operation The L2 ICache sweep operation supports software coherency by enabling data invalidation for a specific address space programmed in the cache registers Invalidation is useful if an instruction in the cache array will not be used and required if the data in t...

Page 430: ...t is low this bit is cleared by hardware at the end of the sweep and then write 0 to the dedicated semaphore While using sweep operation it is recommended to prevent situations in which there is an accesses to the memory space on which sweep operation is executed If such situation does occur however sweep command or an access may override each other a later event overrides an earlier one You shoul...

Page 431: ...ll the L1 ICaches inside the DSP core subsystems are in the debug state The L2 ICache debug mode is initiated by setting a dedicated bit in the cache control registers The L2 ICache state registers are accessible through the internal MBus when the cache debug mode bit is set Any attempt to invoke the cache debug mode while a sweep operation is ongoing is ignored and discarded In addition you shoul...

Page 432: ...ug mode the content of the registers can be read via the MBus This operation also updates the content of the accessed register according to a dedicated counter that selects the appropriate information to be sampled by the register Each state register has a dedicated counter The state registers and their dedicated counters are initialized writing a 0x100 to the L2IC_CR1 CC field and then writing a ...

Page 433: ...ter way 8 index0 ETAG bits in L2IC_B2 re load Read tag array state register way 8 index1 ETAG bits in L2IC_B2 re load Continue Reading from same address Read tag array state register way 8 index 31 ETAG bits in L2IC_B2 re load Read tag array state register way 0 index0 ETAG bits in L2IC_B1 re load way0 index0 L2IC_B1 Continue Reading from same address Table 11 4 Line Replacement Mechanism State Re...

Page 434: ...ter way 1 index0 valid bits in L2IC_B1 re load Read Valid state register way 1 index1 valid bits in L2IC_B1 re load Continue Reading from same address Read Valid state register way 1 index 31 valid bits in L2IC_B1 re load Continue Reading from same address Read Valid state register way 8 index0 valid bits in L2IC_B1 re load Read Valid state register way 8 index1 valid bits in L2IC_B1 re load Conti...

Page 435: ...lected by the byte enable field are not be driven by memory and therefore are not valid 4 After the access is complete hardware clears the L2IC_DBG_ACS INIT bit to enable a new access Use the following steps to write to an array 1 Write the data to be written to L2IC_DBG_DATA up to 32 bits shifted to the right 2 Configure the debug write access by writing the appropriate values to the fields in L2...

Page 436: ...t accesses with a single wait state The M2 memory is fully ECC protected The M2 memory supports partial accesses Automatic read modify write accesses are generated to maintain ECC protection The M2 memory is volatile after reset The 512 KB M2 memory contains four interleaved banks of 128 KB each operating at the system frequency supporting 128 bits data bus width The M2 is a unified memory that st...

Page 437: ...robability of conflict with core accesses and it supports burstable accesses The M3 memory is fully ECC protected The M3 memory uses a novel embedded DRAM eDRAM of 20 macrocells of 4 Mb each to total 80 Mb of user memory with a bidirectional data bus of 128 bit The memory is located between addresses 0xD0000000 and 0xD09FFFFF in the MSC8144E memory map The eDRAM memories operate at 100 MHz frequen...

Page 438: ...rent from the above is sliced to a few accesses each of which complies with the above requirements The eDRAM memory can fix faulty bits by using both redundancy columns and ECC bits There are two redundancy columns in each 4 Mb macrocell and the number of columns needing replacement is determined internally In addition there are 8 ECC bits per 128 bits in the whole memory Using its ECC equation th...

Page 439: ...ge 11 26 L2 ICache Control Register 1 L2IC_CR1 see page 11 26 L2 ICache Control Register 2 L2IC_CR2 see page 11 28 L2 ICache LRM State Register L2IC_LRM see page 11 29 L2 ICache TAG State Register L2IC_TAG see page 11 31 L2 ICache Valid State Register L2IC_VALID see page 11 32 L2 ICache Data Register L2IC_DBG_DATA see page 11 32 L2 ICache Debug Access Register L2IC_DBG_ACS see page 11 33 Note The ...

Page 440: ...e start address of the memory space that correlates to the sweep operation as it appears on msb part of the address bus 7 0 0 Reserved Write to zero for future compatibility L2IC_CR1 L2 ICache Control Register 1 Offset 0x04 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEPA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEPA INV CGS CC CCE Type R W R...

Page 441: ...ep commands apply only if the Cache Command Enable CE bit is set Writing a Cache Command without setting Cache Command Enable bit has no effect 000 Reserved 001 Invalidate Sweep Command 010 Reserved 011 Reserved 100 Initialize State Registers 101 Reserved 110 Reserved 111 Reserved CCE 0 0 Cache Command Enable Writing a 1 to this bit starts the operation specified by the Cache Command field using t...

Page 442: ...thers reserved LB 10 8 111 Cache Way Boundaries Lock The value of this field defines directly the lower and upper boundaries of the cache that are locked or open 000 reserved 001 0 1 010 2 3 011 4 5 100 6 7 101 0 1 2 3 110 4 5 6 7 111 0 1 2 3 4 5 6 7 PFS 7 1 Prefetch Select Enables disables the prefetch operation 0 Prefetch disabled 1 Prefetch selected 6 4 0 Reserved Write to zero for future compa...

Page 443: ...obal lock mode active CE 0 0 Cache Memory Enabled Indicates whether the two L2 cache memory modules are enabled or disabled At reset deassertion the two modules are disabled Once the cache memory is enabled it may be disabled only by reset In disable mode the clock inside each memory module is disabled and power is saved Note This is a sticky bit 0 Cache memory disabled 1 Cache memory enabled L2IC...

Page 444: ...d 1 Cache line valid 7 0 Reserved Write to zero for future compatibility PLRUB0 6 0 0 PLRU Bits 0 Holds the state bits for indexes 4 i i is an integer 0 Cache line not valid 1 Cache line valid Table 11 10 PLRU Replacement Way Selection PLRU Bits Way Selected for Replacement B0 0 B1 0 B3 0 L0 0 0 1 L1 0 1 B4 0 L2 0 1 1 L3 1 B2 0 B5 0 L4 1 0 1 L5 1 1 B6 0 L6 1 1 1 L7 Table 11 9 L2IC_LRM Bit Descript...

Page 445: ... Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAG Type R Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 11 11 L2IC_TAG Bit Descriptions Name Reset Description Settings 31 24 0xFF Reserved Write to ones for future compatibility TVB 23 0 Tag Valid Bit Indicates whether the whole cache line is valid or not 0 Cache line not valid 1 Cache line valid 22 18 0 Reserved Writ...

Page 446: ...3 2 1 0 VALID Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 12 L2IC_VALID Bit Descriptions Name Reset Description Settings 31 16 0 Reserved Write to zero for future compatibility VALID 15 0 0 VBR Valid This field indicates the status of the valid bits of each of the reflected VBRs The reflected VBRs are determined by a dedicated counter 0 VBR not valid 1 VBR valid L2IC_DBG_DATA L2 ICache D...

Page 447: ...gs 31 25 0 Reserved Write to zero for future compatibility INIT 24 0 Debug Access Initiation Initiates a read or write access to the cache array in debug mode The data should be valid before setting this bit The bit is ignored except in debug mode The bit clears on hardware cycle after it is set by software 0 No access 1 Initiate access RW 23 0 Read Write Indicates whether the access is a read or ...

Page 448: ...Byte offset within the long bits 1 0 To make an aligned access to the DBG_ACS_SIZE use only the following options For DBG_ACS_SIZE 0b10 long the byte offset must 0b00 only For DBG_ACS_SIZE 0b01 word the byte offset can be 0b00 or 0b10 For DBG_ACS_SIZE 0b00 byte the byte offset can be 0b00 0b01 0b10 or 0b11 L2IC_CSA L2 ICache Cacheable Area Start Address Offset 0xC04 Bit 31 30 29 28 27 26 25 24 23 ...

Page 449: ... Address Offset 0xC44 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EA Type R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 11 16 L2IC_CEA Bit Descriptions Name Reset Description Settings 31 20 0 Reserved Write to zero for future compatibility EA 19 0 oxFFFFF End Address Contains the 20 msbs of the L2...

Page 450: ...oper operation do not enable the L2 ICache cacheable area until after the cacheable window is defined in L2IC_CSA and L2IC_CEA This register is reset by a soft reset Table 11 17 defines the L2IC_CEN bit fields L2IC_CEN L2 ICache Cacheable Area Enable 0xC84 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DE...

Page 451: ...lock of the L2 ICache Every access to L2 ICache should start and end in the same cache line so the CLASS can handle the interleave between the L2 instruction cache banks Accesses from the DSP core subsystem toward memory through the L2 ICache must be of one VBR or with a burst of 4 VBRs byte count of 64 You must program this limitation into the MMU in the DSP core subsystem to ensure this operatio...

Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...

Page 453: ...including ECC error injection support rapid system debug Figure 12 1 shows a high level view of the DDR memory controller with its associated interfaces Figure 12 1 DDR SDRAM Memory Controller Block Diagram Address from DDR SDRAM Data from Data from DDR SDRAM Data Signals RMW ECC Request from Row Physical Bank FIFO SDRAM Address Open Row Address EN EN Data Qualifiers Clocks To Error MA 0 15 MBA 0 ...

Page 454: ...errors within the 32 bit or 16 bit data bus and detects all errors within a nibble The controller allows as many as 16 pages to be open simultaneously The amount of time in clock cycles the pages remain open is programmed via the DDR_SDRAM_INTERVAL BSTOPRE bit see Table 12 27 on page 12 49 Read and write accesses to memory are burst oriented accesses start at a selected location and continue for f...

Page 455: ...ome typical signal connections Figure 12 3 Typical DDR SDRAM Interface Signals Logical Bank 0 Logical Bank 1 Logical Bank 2 Logical Bank 3 Multiplex Mask Read Data Latch Data Out Registers Data In Registers Data Bus ADDR COMMAND DQM BA1 BA0 CKE MCK MCK MCS MRAS MCAS MWE Control SDRAM A 12 0 Write Enable DQ 7 0 DQS 64 M 1 Byte CK Command Bus 512 Mbit BA 1 0 Data Data 8 ADDR MRAS MCAS MWE MCS DM CKE...

Page 456: ... Operation The DDR memory controller supports many different DDR SDRAM configurations Sixteen multiplexed address signals and three logical bank select signals support device densities from 64 Mb to 4 Gb The DDR SDRAM physical banks can be built from directly attached memory devices The data path to individual physical banks is 32 or 16 bits wide 40 or 24 bits with ECC The DDR memory controller su...

Page 457: ... MCS1 Bank 1 8M 40 32 MB To All SDRAM Devices Memory Data Bus and Strobes Bank 0 8M 40 32 MB CAS CS RAS CKE CLK DM A 11 0 2Mx8 SDRAM DQ 7 0 BA 1 0 CAS CS RAS CKE CLK DM A 11 0 2Mx8 SDRAM DQ 7 0 BA 1 0 CAS CS RAS CKE CLK DM A 0 11 2Mx8 SDRAM DQ 0 7 BA 0 1 CAS CS RAS CKE CK DM A 11 0 8M 8 SDRAM DQ 7 0 BA 1 0 MDQ 8 15 MDQ 16 23 MDQ 24 31 MDQS0 MDQS MDQS3 MDQS4 MDQS MDQS0 MDQS MDQS3 MDQS 0 4 3 MCK 0 2...

Page 458: ...memory controller Note DDR SDRAM is limited to 30 total address bits Table 12 1 Byte Lane to Data Relationship for a 32 Bit Memory Interface Data Byte Lane Data Bus Mask Data Bus Strobe Data Bus 32 Bit Mode 0 MSB MDM0 MDQS0 MDQ 0 7 1 MDM1 MDQS1 MDQ 8 15 2 MDM2 MDQS2 MDQ 16 23 3 LSB MDM3 MDQS3 MDQ 24 31 Table 12 2 Byte Lane to Data Relationship16 Bit Memory Interface Data Byte Lane Data Bus Mask Da...

Page 459: ...opriate MCSx signal for memory accesses according to the bank starting and ending addresses The memory banks do not have to be mapped to a contiguous address space 12 1 3 DDR SDRAM Address Multiplexing Table 12 5 and Table 12 6 show the address bit encodings for each DDR SDRAM configuration The address at the memory controller signals MA 15 0 use MA15 as the MSB and MA0 as the LSB Also MA10 is the...

Page 460: ... 2 1 0 MBA 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 15 x 11 x 2 MRAS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 1 0 MCAS 11 9 8 7 6 5 4 3 2 1 0 15 x 10 x 2 MRAS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 14 x 11 x 2 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 1 0 MCAS 11 9 8 7 6 5 4 3 2 1 0 14 x 10 x 2 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 13 x 11 x 2 MRAS 12 ...

Page 461: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 16 x 10 x 3 MRAS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 15 x 10 x 3 MRAS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 14 x 10 x 3 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 14 x 10 x 2 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBA 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 13 x 10 x 3 MRAS 12 11 10 ...

Page 462: ...ion for reading another row in the memory array performing another activate command Precharge must occur after read or write if the row address changes on the next open page mode access Read Latches column address and transfers data from the selected sense amplifier to the output buffer as determined by the column address During each succeeding clock edge additional data is driven without addition...

Page 463: ... mode register set command during system initialization Parameters such as mode register data MCAS latency burst length and burst type are set by software in DDR_SDRAM_MODE SDMODE and transferred to the SDRAM array by the DDR memory controller after DDR_SDRAM_CFG MEMEN is set If DDR_SDRAM_CFG BI is set to bypass the automatic initialization software can configure the mode registers via the DDR_SDR...

Page 464: ...nterface Timing Intervals Timing Intervals Definition Register Page ACTTOACT The number of clock cycles from a bank activate command to another bank activate command within a physical bank This interval is listed in the AC specifications of the SDRAM as tRRD DDR SDRAM Timing Configuration Register 1 TIMING_CFG_1 page 12 38 ACTTOPRE Activate to Precharge Interval The number of clock cycles from an ...

Page 465: ...DDR SDRAM Interval Configuration Register page 12 49 REFREC Refresh Recovery Time The number of clock cycles from the refresh command until an activate command is allowed This interval is listed in the AC specifications of the SDRAM as tRFC DDR SDRAM Timing Configuration Register 1 TIMING_CFG_1 page 12 38 WR_DATA_DELAY Write Data Delay Provides different options for the timing between a write comm...

Page 466: ...ds These figures assume that DDR_SDRAM_CLK_CNTL CLKADJ 0100 set to 1 2 DRAM cycle the additive latency is 0 DRAM cycles and the write latency is 1 DRAM cycle for DDR1 ar Figure 12 5 DDR SDRAM Burst Read Timing ACTTORW 3 MCAS Latency 2 Figure 12 6 DDR SDRAM Single Beat Word Write Timing ACTTORW 3 ACTTORW ROW COL SDRAM Clock MCS MCAS MA 15 0 MDQ 0 31 MWE MRAS MDQS COL D1 D2 D3 D1 D2 D0 D3 D0 0 1 2 3...

Page 467: ...stem Distribute MCK MCK equally between chips to ensure similar load delay PCB traces for DDR clock signals should be short all on the same layer and of equal length and loading DDR SDRAM manufacturers provide details on PCB layout and termination issues Figure 12 8 DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs ROW COL SDRAM clock MCS0 MCAS MA 15 0 MDQ 0 31 MWE MRAS MDQS MDM 0 3 0 COL MCS...

Page 468: ...MING_CFG_2 WRITE_DATA_DELAY for data and DQS The DDR SDRAM specification requires that DQS be received no sooner than 75 percent and no later than 125 percent of an SDRAM clock period from the capturing clock edge of the command address at the SDRAM The TIMING_CFG_2 WRITE_DATA_DELAY parameter can be used to meet this timing requirement for a variety of system configurations ranging from a system w...

Page 469: ... reached If a memory transaction is in progress when the refresh interval is reached the refresh cycle waits for the transaction to complete In the worst case the refresh cycle must wait the number of bus clock cycles required by the longest programmed access To ensure that the latency caused by a memory transaction does not violate the device refresh period it is recommended that the programmed v...

Page 470: ... the refresh interval to be set to a larger value Note The MSC8144 will initiate three cycles of Precharge ALL commands and three cycles of Refresh commands although there are only two banks chip select available 12 3 4 1 DDR SDRAM Refresh Timing Refresh timing for the DDR SDRAM is controlled by the programmable timing parameter TIMING_CFG_1 REFREC which specifies the number of memory bus clock cy...

Page 471: ...is no system memory activity The CKE pin is deasserted when both conditions are met no memory refreshes are scheduled no memory accesses are scheduled The CKE pin is reasserted when a new access or refresh is scheduled or the dynamic power mode is disabled This mode is controlled with DDR_SDRAM_CFG DYN_PWR Dynamic power management mode offers tight control of the memory system power consumption by...

Page 472: ...13 DDR SDRAM Self Refresh Entry Timing Figure 12 14 DDR SDRAM Self Refresh Exit Timing SDRAM clock MCS MCAS MA 15 0 MDQ 0 31 MWE MRAS MDQS High Impedance MCKE 0 1 2 3 4 5 6 7 8 9 10 11 12 High Impedance 200 cycles SDRAM Clock MCS MCAS MA 15 0 MDQ 0 31 MWE MRAS MDQS 0 1 2 3 4 5 6 7 202 203 204 205 206 ...

Page 473: ...s or 16 bits interface accordingly For transfer sizes other than four beats the data transfers are still in four beat bursts If ECC is enabled and either the access is not word aligned or the size is not a multiple of a word a full read modify write is performed for a write to SDRAM If ECC is disabled or the access is word aligned with a size that is a multiple of a word the data masks MDM 0 5 can...

Page 474: ... or disabled for each chip select In open page mode the DDR memory controller retains the currently active SDRAM page by not issuing a precharge command The page remains opens until one of the following conditions occurs Refresh interval is met The user programmable DDR_SDRAM_INTERVAL BSTOPRE value is exceeded There is a logical bank row collision with another transaction that must be issued Page ...

Page 475: ...d for the merged data The data and ECC code is then written to memory If a multi bit error is detected on the read the transaction completes the read modify write to keep the DDR memory controller from hanging However the corrupt data is masked on the write so the original contents in SDRAM remain unchanged The syndrome encoding for the ECC code are shown in Table 12 10 and Table 12 11 Table 12 10...

Page 476: ...pletes the transaction normally If a multi bit error is detected for a read the DDR memory controller logs the error and generates the critical interrupt if enabled as described in Table 12 41 on page 12 59 The DDR memory controller also detects a memory select error which causes the DDR memory controller to log the error and generate a critical interrupt if enabled as described in Table 12 40 on ...

Page 477: ... in the memory interface configuration registers listed in Table 12 13 Note 1 Before initiating the DDR controller registers the DDR_GCR DDR_VSEL should be programmed according to the DDR device connected to the MSC8144 For DDR1 devices the DDR_GCR DDR_VSEL 0 reset value for DDR2 devices the DDR_GCR DDR_VSEL 1 Programming the correct value is essential for the correct Table 12 12 Memory Controller...

Page 478: ...G_CFG_0 Read to Write Turn Around RWT Write to Read Turn Around WRT Read to Read Turn Around RRT Write to Write Turn Around WWT Active Power Down Exit Timing ACT_PD_EXIT Precharge Power Down Exit Timing PRE_PD_EXIT ODT Power Down Exit Timing PDT_PD_EXIT Mode Register Set Cycle Time MRS_CYC Table 12 19 on page 12 35 Timing Configuration 1 Register TIMING_CFG_1 Precharge to Activate Interval PRETOAC...

Page 479: ...eshes NUM_PR DRAM Data Initialization D_INIT Table 12 23 on page 12 45 DDR SDRAM Mode Configuration Register DDR_SDRAM_MODE Extended SDRAM Mode ESDMODE SDRAM Mode SDMODE Table 12 24 on page 12 46 DDR SDRAM Mode Configuration 2 Register DDR_SDRAM_MODE_2 Extended SDRAM Mode 2 ESDMODE2 Extended SDRAM Mode 3 ESDMODE3 Table 12 25 on page 12 47 DDR SDRAM Interval Configuration Register DDR_SDRAM_INTERVA...

Page 480: ...the memory used tras Table 12 20 on page 12 38 DDR2 ACTTORW Activate to Read Write Timing DDR1 Configure according to the specifications for the memory used trcd Table 12 20 on page 12 38 DDR2 CASLAT CAS Latency DDR1 Configure to the desired CAS latency Table 12 20 on page 12 38 DDR2 REFREC Refresh Recovery DDR1 Configure along with the Extended Refresh Recovery to the specifications for the memor...

Page 481: ...ing to the specifications for the memory used tcke FOUR_ACT Window for Four Activates DDR1 Configure to 0001 Table 12 21 on page 12 40 DDR2 Configure according to the specifications for the memory used tfaw Applicable for 8 logical banks 2T_EN 2T Timing Enable DDR1 In heavily loaded systems this bit can be set to 1 to gain extra timing margin on the interface at the cost of address command bandwid...

Page 482: ...ld descriptions very carefully The DDR memory controller registers are as follows Chip Select Memory Bounds Register CSx_BNDS page 12 32 Chip Select Configuration Register CSx_CONFIG page 12 33 DDR SDRAM Extended Refresh Recovery Register TIMING_CFG_3 page 12 34 DDR SDRAM Timing Configuration 0 Register TIMING_CFG_0 page 12 35 DDR SDRAM Timing Configuration 1 Register TIMING_CFG_1 page 12 38 DDR S...

Page 483: ...ror Injection Mask ECC Register DDR_ERR_INJECT page 12 55 Memory Data Path Read Capture High Register CAPTURE_DATA_HI page 12 56 Memory Data Path Read Capture Low Register CAPTURE_DATA_LO page 12 57 Memory Data Path Read Capture ECC Register CAPTURE_ECC page 12 57 Memory Error Detect Register ERR_DETECT page 12 58 Memory Error Disable Register ERR_DISABLE page 12 59 Memory Error Interrupt Enable R...

Page 484: ...to SAx should be 0x080 If the DDR SDRAM end address is 0x43FF_FFFF the value written to EAx should be 0x087 CSx_BNDS Chip Select Bounds Register CS0_BNDS Offset 0x0000 CS1_BNDS 0x0008 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SAx Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EAx Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 16 CSx_...

Page 485: ...0 0 Table 12 17 CSx_CONFIG Field Descriptions Bit Reset Description Settings CS_x_EN 31 0 Chip Select x Enable Enables disables chip select 0 Chip select x is not active 1 Chip select x is active and assumes the state set in CSx_BNDS 30 24 0 Reserved Write to zero for future compatibility AP_x_EN 23 0 Chip Select x Auto Precharge Enable Specifies when auto precharged is enabled for this specific c...

Page 486: ...al bank bits 10 11 Reserved 13 11 0 Reserved Write to zero for future compatibility ROW_ BITS_CS_ x 10 8 0 Number of Row Bits Specifies the number of row bits for SDRAM on chip select x see Table 12 5 and Table 12 6 for details 000 12 row bits 001 13 row bits 010 14 row bits 011 15 row bits 100 16 row bits 101 111 Reserved 7 3 0 Reserved Write to zero for future compatibility COL_ BITS_CS_ x 2 0 0...

Page 487: ... 0 clock cycles 001 16 clock cycles 010 32 clock cycles 011 48 clock cycles 100 64 clock cycles 101 80 clock cycles 110 96 clock cycles 111 112 clock cycles 15 0 0 Reserved Write to zero for future compatibility TIMING_CFG_0 DDR SDRAM Timing Configuration Register 0 Offset 0x0104 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RWT WRT RRT WWT ACT_PD_EXIT PRE_PD_EXIT Type R W R R W R R W Reset ...

Page 488: ...n Around Specifies how many extra cycles to add between writes to different chip selects By default 2 cycles are required between write commands to different chip selects If 00 is selected the DDR Controller will use a predefined value 2 clocks for the turnaround selecting a value other than 00 adds extra cycles to this predefined value according to the selection 00 0 clock cycles 01 1 clock cycle...

Page 489: ...clock cycles 1101 13 clock cycles 1110 14 clock cycles 1111 15 clock cycles 7 4 0 Reserved Write to zero for future compatibility MRS_CYC 3 0 0b0101 Mode Register Set Cycle Time tMRD Specifies the number of clock cycles that must pass between a Mode Register Set command and another command The default is 5 clock cycles 0000 Reserved 0001 1 clock 0010 2 clock cycles 0011 3 clock cycles 0100 4 clock...

Page 490: ...ogrammed for proper operation of the DDR Controller 000 Reserved 001 1 clock 010 2 clock cycles 011 3 clock cycles 100 4 clock cycles 101 5 clock cycles 110 6 clock cycles 111 7 clock cycles ACTTOPRE 27 24 0 Activate to Precharge Interval tRAS Specifies the minimum number of clock cycles between an activate command and a precharge command This number is calculated from the AC specifications of the...

Page 491: ...cycles between a refresh command and an activate command This value can be calculated by referring to the AC specification of the SDRAM device The AC specification indicates a maximum refresh to activate interval in nanoseconds This field is concatenated with TIMING_CFG_3 REFR to obtain a 7 bit value for the total refresh recovery Note that hardware adds an additional 8 clock cycles to the final 7...

Page 492: ... clock cycles between the last write data pair and the subsequent read command to the same physical bank This field must be programmed for proper operation of the DDR Controller 000 Reserved 001 1 clock cycle 010 2 clock cycles 011 3 clock cycles 100 4 clock cycles 101 5 clock cycles 110 6 clock cycles 111 7 clock cycles TIMING_CFG_2 DDR SDRAM Timing Configuration Register 2 Offset 0x010C Bit 31 3...

Page 493: ... RL 9 2 10101 RL 19 4 10110 11110 Reserved 11111 Automatic Calibration recommended 22 0 Reserved Write to zero for future compatibility WR_LAT 21 19 0 Write Latency Note that the total write latency for DDR2 is equal to WR_LAT ADD_LAT The Write Latency for DDR1 is 1 This field must be programmed for proper operation of the DDR Controller 000 Reserved 001 1 clock cycle 010 2 clock cycles 011 3 cloc...

Page 494: ...00 0 clock delay 001 1 4 clock delay 010 1 2 clock delay 011 3 4 clock delay 100 1 clock delay 101 5 4 clock delay 110 3 2 clock delay 111 Reserved 9 0 Reserved Write to zero for future compatibility CKE_PLS 8 6 0 Minimum CKE Pulse Width tCKE Can be set to 001 for DDR1 This field must be programmed for proper operation of the DDR Controller 000 Reserved 001 1 clock cycle 010 2 clock cycles 011 3 c...

Page 495: ...1Reserved 010 DDR1 SDRAM 011 DDR2 SDRAM 100 111Reserved 23 22 0 Reserved Write to zero for future compatibility DYN_PWR 21 0 Dynamic Power Management Mode Enabled disables dynamic power management mode When this bit is set and there is no on going memory activity the SDRAM CKE signal is deasserted 0 Dynamic power management mode is disabled 1 Dynamic power management mode is enabled 20 0 Reserved ...

Page 496: ...use hangs of the cores and other initiator 0 DDR controller accepts new transactions 1 DDR controller finishes any remaining transactions and then halts until software clears this bit BI 0 0 Bypass Initialization Specifies the conditions for initialization When this bit is set software is responsible for initializing memory through the SMCFG2 register If software is initializing memory the MHALT b...

Page 497: ...used 01 Differential DQS signals are used for DDR2 support 10 Reserved 11 Reserved 25 23 0 Reserved Write to zero for future compatibility ODT_CFG 22 21 0 ODT Configuration Defines how ODT is driven to the on chip I O See Table 12 49 for the definition of the impedance value that will be used 00 Never assert ODT to internal I O 01 Assert ODT to internal I O only during writes to DRAM 10 Assert ODT...

Page 498: ...2 11 10 9 8 7 6 5 4 3 2 1 0 SDMODE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 24 DDR_SDRAM_MODE Bit Descriptions Bit Refresh Description ESDMODE 31 16 0 Extended SDRAM Mode Specifies the initial value loaded into the DDR SDRAM extended mode register The range of legal values is specified by the DDR SDRAM manufacturer When this value is driven onto the address bus during DDR SDRAM init...

Page 499: ... and meaning of legal values is specified by the DDR SDRAM manufacturer When this value is driven onto the address bus during the DDR SDRAM initialization sequence MA0 presents the LSB bit of ESDMODE2 which corresponds to DDR_SDRAM_MODE_2 bit 16 The MSB of the SDRAM extended mode 2 register value must be stored at DDR_SDRAM_MODE_2 bit 31 ESDMODE3 15 0 0 Extended SDRAM Mode 3 Specifies the initial ...

Page 500: ...NDED MODE REGISTER SET 3 command 30 29 0 Reserved Write to zero for future compatibility CSSEL 28 0 Select for Chip Select Specifies the chip select to drive active due to any command forced by software in DDR_SDRAM_MD_CNTL 0 Chip select 0 is active 1 Chip select 1 is active 27 0 Reserved Write to zero for future compatibility MDSEL 26 24 0 Mode Register Select Specifies the value to present to th...

Page 501: ...gh value 11 Reserved 19 16 0 Reserved Write to zero for future compatibility MDV 15 0 0 Mode Register Value Specifies the value to present to the memory address pins of the DDR controller during the MODE REGISTER SET EXTENDED MODE REGISTER SET EXTENDED MODE REGISTER SET 2 or EXTENDED MODE REGISTER SET 3 command DDR_SDRAM_INTERVAL DDR SDRAM Interval Configuration Offset 0x0124 Register Bit 31 30 29...

Page 502: ...rge bank command as soon as possible If BSTOPRE has a value of zero the DDR memory controller uses auto precharge read and write commands rather than operating in page mode This is called global auto precharge mode DDR_DATA_INIT DDR SDRAM Data Initialization Register Offset0x0128 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVAL Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12...

Page 503: ...NTL Bit Descriptions Bit Reset Description Settings 31 27 0 Reserved Write to zero for future compatibility CLK_ADJUST 26 23 0 Clock Adjust Specifies when the clock is launched in relationship to the address command 0000 Clock launched and aligned with address command 0001 Clock launched 1 8 applied cycle after address command 0010 Clock launched 1 4 applied cycle after address command 0011 Clock ...

Page 504: ...ed for the data strobe to data skew adjustment and automatic CAS to preamble calibration at power on reset If used during initialization sequence this address will be written during the initialization sequence DDR_INIT_EN DDR SDRAM Initialization Address Enable Register Offset0x014C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UIA Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 1...

Page 505: ...Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPMJ IPMN Type R Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Table 12 32 DDR_IP_REV1 Bit Descriptions Bit Reset Description IPID 31 16 0x0002 IP Block ID For the DDR controller IPMJ 15 8 0x02 Major Revision IPMN 7 0 0x00 Minor Revision DDR_IP_REV2 DDR SDRAM IP Block Revision 2 Register Offset0x0BFC Bit 31 30 29 28 27 ...

Page 506: ... 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ELSB Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 34 DDR_ERR_INJECT_HI Bit Descriptions Bit Reset Description EMSB 31 24 0 Error Injection Mask for Bits 0 7 Tests ECC by forcing errors on the high bytes of the data path Setting a bit causes the corresponding data path bit to be inverted during memory bus writes 23 16 0 Reserved Write to...

Page 507: ... 0 0 0 Table 12 35 DDR_ERR_INJECT_LO Bit Descriptions Bit Reset Description EIMSB 31 24 0 Error Injection Mask for Bits 16 23 Tests ECC by forcing errors on the low bytes of the data path Setting a bit causes the corresponding data path bit to be inverted during memory bus writes 23 16 0 Reserved Write to zero for future compatibility EILSB 15 8 0 Error Injection Mask for Bits 24 31 Tests ECC by f...

Page 508: ... disabled 1 Error injection enabled This applies to the data mask bits and to the ECC mask bits EEIM 7 0 0 ECC Error Injection Mask 0 7 Setting a mask bit causes the corresponding ECC bit to be inverted during memory bus writes CAPTURE_DATA_HI DDR SDRAM Memory Data Path Offset 0x0E20 Read Capture Data High Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CDHMSB Type R W R Reset 0 0 0 0...

Page 509: ...LMSB Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CDLLSB Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 38 CAPTURE_DATA_LO Bit Descriptions Bit Reset Description CDLMSB 31 24 0 Error Capture Low Data Path Captures bits 16 23 of the data path when errors are detected 23 16 0 Reserved Write to zero for future compatibility CDLlSB 15 8 0 Error ...

Page 510: ...rrors are detected 0 7 ERR_DETECT DDR SDRAM Memory Error Detect Register Offset0x0E40 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MME Type W1C R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACE MBE SBE MSE Type R W1C R W1C R W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 40 ERR_DETECT Bit Descriptions Bit Reset Description Settings MME 31 0 Multiple M...

Page 511: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACED MBED SBED MSED Type R R W R R W R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 41 ERR_DISABLE Bit Descriptions Bit Reset Description Settings 31 8 0 Reserved Write to zero for future compatibility ACED 7 0 Automatic Calibration Error Disable Enables di...

Page 512: ...INT_EN Bit Descriptions Bit Reset Description Settings 31 8 0 Reserved Write to zero for future compatibility ACEE 7 0 Automatic Calibration Error Interrupt Enable Specifies whether automatic calibration errors generate interrupts 0 Calibration errors cannot generate interrupts 1 Calibration errors generate interrupts 6 4 0 Reserved Write to zero for future compatibility MBEE 3 0 Multiple Bit ECC ...

Page 513: ... 6 5 4 3 2 1 0 TTYP VLD Type R R W R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 43 CAPTURE_ATTRIBUTES Bit Descriptions Bit Reset Description Settings 31 30 0 Reserved Write to zero for future compatibility BNUM 29 28 0 Data Beat Number Captures the data beat number for the detected error This bit is relevant only for ECC errors 27 14 0 Reserved Write to zero for future compatibility TTYP 1...

Page 514: ...ERR_SBE CAPTURE_ADDRESS DDR SDRAM Memory Error Address Offset 0x0E50 CaptureRegister Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CADDR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CADDR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 44 CAPTURE_ADDRESS Bit Descriptions Bit Reset Description Settings CADDR 31 0 0 Captured Address Captures ...

Page 515: ...ndition is reported 15 8 0 Reserved Write to zero for future compatibility SBEC 7 0 0 Single Bit Error Counter Indicates the number of single bit errors detected and corrected since the last error report If single bit error reporting is enabled an error is reported when this value equals SBET SBEC is automatically cleared when the threshold value is reached DDR_STOP_STATUS DDR SDRAM DDR Status Off...

Page 516: ...DR controller not ready to stop 1 DDR controller ready to stop DDR_PWR DDR SDRAM Power Control Register Offset 0x1004 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DQSL STOP Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 47 DDR_PWR Bit Descriptions Bit Reset Description Settings 31 2 0 Reserved ...

Page 517: ...2 1 0 1OE 0OE Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 48 MDIC_OE_CONT Bit Descriptions Bits Reset Description Setting 31 2 0 Reserved Write to zero for future compatibility MDIC1_OE 1 0 Output Enable for MDIC_1 Forces the output enable to be set only if TERM_OCD_ODT_CONT DCOV is also set 0 if TERM_OCD_ODT_CO NT DCOV is set force MDIC1_OE to disable 1 if TERM_OCD_ODT_CO NT DCOV is...

Page 518: ...during initialization enabled 1 Bit Deskew during initialization disabled DCOV 13 Driver Comp Override Enable for the software override of the driver impedance 0 Software override for driver impedance disabled 1 Software override for driver impedance enabled DCEN 12 Driver Comp Enable Enable bit for the driver impedance hardware calibration 0 Hardware calibration of driver impedance disabled 1 Har...

Page 519: ...er Offset 0x1010 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INIT Type R R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 50 CLK_RATIO_CONT Bit Descriptions Bit Reset Description Settings 31 2 0 Reserved Write to zero for future compatibility INIT 1 0 Specifies whether the CLASS128 clock frequency is...

Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...

Page 521: ...ble interrupts VNMI towards the cores as well as generates interrupts to external devices 2 General configuration block Concentrates and routes rare and debug interrupts to the SC3400 cores 3 Embedded programmable interrupt controller EPIC Concentrates all the interrupt directed at the associated core and dispatches the highest priority interrupt to the SC3400 core Although there are various inter...

Page 522: ...Description VIRQ Num Destination VIRQ_0 Connected to Virtual Interrupt 0 at SC3400 VIRQ_1 Connected to Virtual Interrupt 1 at SC3400 VIRQ_2 Connected to Virtual Interrupt 2 at SC3400 VIRQ_3 Connected to Virtual Interrupt 3 at SC3400 VIRQ_4 Connected to Virtual Interrupt 4 at SC3400 VIRQ_5 Connected to Virtual Interrupt 5 at SC3400 VIRQ_6 Connected to Virtual Interrupt 6 at SC3400 VIRQ_7 Connected ...

Page 523: ...errupt Groups The general configuration block generates 4 interrupts based on the groups of ORed interrupts described in Table 13 2 The general configuration block also routes and records the status of the VNMIs generated by the GIC Table 13 2 General Configuration Block Interrupt Sources TDM Debug General Watch Dog Timer TDM 0 Rx error CLASS 0 overrun M2_0 ECC error Watch Dog Timer 0 TDM 0 Tx err...

Page 524: ...ternal interrupt inputs in the MSC8144E NMI_OUT is asserted whenever one of the following conditions is fulfilled NMI is asserted VIRQ_17 is asserted The system watchdog timer interrupt SWT4 is asserted These conditions are not maskable by software INT_OUT is asserted when VIRQ_16 is asserted Table 13 3 MSC8144E External Interrupt Pins Name GPIO Direction NMI N A In NMI_OUT N A Out INT_OUT N A Out...

Page 525: ...uted to the cores via the general configuration block for example virtual non maskable interrupt 0 4 Interrupts that represent multiple interrupt sources and are routed to the cores via the General Configuration Block for example parity error from TDM 0 3 interrupt Figure 13 1 outlines the flow for handling the various types of interrupts Figure 13 1 Interrupt Handling Flow Core Interrupted Interr...

Page 526: ...routing is set by the EPIC see the MSC8144 SC3400 DSP Core Subsystem Reference Manual for details Table 13 4 MSC8144E Interrupt Table Interrupt Description IRQ index Level Edge TDM TDM 0 Rx first threshold 48 TDM 0 Rx second threshold 49 TDM 0 Tx first threshold 50 TDM 0 Tx second threshold 51 TDM 1 Rx first threshold 52 TDM 1 Rx second threshold 53 TDM 1 Tx first threshold 54 TDM 1 Tx second thre...

Page 527: ... RapidIO doorbell out 0 89 Serial RapidIO general error 90 Ethernet 1 Ethernet 1 all 91 Ethernet 1 Rx 0 92 Ethernet 1 Rx 1 93 Ethernet 1 Rx 2 94 Ethernet 1 Rx 3 95 Ethernet 1 Rx 4 96 Ethernet 1 Rx 5 97 Ethernet 1 Rx 6 98 Ethernet 1 Rx 7 99 Ethernet 1 Tx 0 100 Ethernet 1 Tx 1 101 Ethernet 1 Tx 2 102 Ethernet 1 Tx 3 103 Ethernet 1 Tx 4 104 Ethernet 1 Tx 5 105 Ethernet 1 Tx 6 106 Ethernet 1 Tx 7 107 ...

Page 528: ...M global 2 130 ATM global 3 131 ATM global red line 132 ATM interrupt queue 0 overflow 133 ATM interrupt queue 1 overflow 134 ATM interrupt queue 2 overflow 135 ATM interrupt queue 3 overflow 136 ATM transmit rate underrun 137 QUICC Engine Subsystem QUICC Engine module critical 140 QUICC Engine module regular 141 DMA DMA channel 0 EOB 144 DMA channel 1 EOB 145 DMA channel 2 EOB 146 DMA channel 3 E...

Page 529: ...Timer 1 Channel 3 167 Timer 2 Timer 2 Channel 0 168 Timer 2 Channel 1 169 Timer 2 Channel 2 170 Timer 2 Channel 3 171 Timer 3 Timer 3 Channel 0 172 Timer 3 Channel 1 173 Timer 3 Channel 2 174 Timer 3 Channel 3 175 UART UART all 176 Global Interrupt Controller Virtual Interrupt 0 177 Virtual Interrupt 1 178 Virtual Interrupt 2 179 Virtual Interrupt 3 180 Virtual Interrupt 4 181 Virtual Interrupt 5 ...

Page 530: ... 1 194 Virtual Non Maskable Interrupt 2 195 Virtual Non Maskable Interrupt 3 196 I2 C I2C all 213 External IRQs IRQ0 226 IRQ1 227 IRQ2 228 IRQ3 229 IRQ4 230 IRQ5 231 IRQ6 232 IRQ7 233 IRQ8 234 IRQ9 235 IRQ10 236 IRQ11 237 IRQ12 238 IRQ13 239 IRQ14 240 IRQ15 241 NMI 242 General Configuration Block ORed TDM interrupts 243 ORed Debug Interrupts 244 ORed General Interrupts 245 ORed Watch Dog Timer Int...

Page 531: ...cenarios and resulting restrictions on the user OCN DMA Channel 0 Interrupt 248 Channel 1 Interrupt 249 Channel 2 Interrupt 250 Channel 3 Interrupt 251 General Hardware Interrupt 252 Table 13 5 Restrictions Listed by Interrupt Source EPIC Index Event Problematic scenario Restriction 226 IRQ0 External source generates a IRQ NMI as a response to a Core read access from the DDR PCI The peripheral mus...

Page 532: ... number and correct the soft error DDR single double ECC error DSP core is reading an address in DDR with soft error Read the address from the DDR controller and correct the soft error For single ECC errors the threshold can be set to more than one error DDR access to an address that does not hit any DDR configuration space DSP core is reading an address in DDR that does not hit any DDR configurat...

Page 533: ...se a base address of 0xFFF27000 13 5 1 1 Virtual Interrupt Generation Register VIGR VIGR generates virtual interrupts according to the written data The VIRQ generated corresponds to the combination of VIRQNUM_H VIRQNUM_L A read from VIGR returns all zeros Notice that the supported values of VIRQNUM_H VIRQNUM_L are 0 to 19 VIGR Virtual Interrupt Generation Register Offset0x00 Bit 31 30 29 28 27 26 ...

Page 534: ... generates a virtual non maskable interrupt to the SC3400 cores The VNMI generated corresponds with the number written to VNMINUM A read from VNMIGR returns all zeros VISR Virtual Interrupt Status Register Offset 0x08 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VS19 VS18 VS17 VS16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VS15 VS14 VS13 VS12 V...

Page 535: ... General Interrupt Register 1 GIR1 GIR1 includes interrupt status of ECC events of M2 Those bits are sticky and cleared by writing 1 The GIR1 is reset by a hard reset event All bits are cleared on reset Write accesses to this register can be performed only in supervisor mode GIR1 General Interrupt Register 1 Offset 0x40 Bit 31 30 29 28 27 26 25 24 Type R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 ...

Page 536: ...M2 Block 2 ECC Error Interrupt Asserted when ECC error is reported by M2_2 0 Interrupt not asserted 1 Interrupt asserted M2_1_ECC 1 M2 Block 1 ECC Error Interrupt Asserted when ECC error is reported by M2_1 0 Interrupt not asserted 1 Interrupt asserted M2_0_ECC 0 M2 Block 0 ECC Error Interrupt Asserted when ECC error is reported by M2_0 0 Interrupt not asserted 1 Interrupt asserted GIER1_0 General...

Page 537: ...upt disabled 1 Interrupt enabled M2_2_ECC_EN 2 M2 Block 2 ECC Error Enable 0 Interrupt disabled 1 Interrupt enabled M2_1_ECC_EN 1 M2 Block 1 ECC Error Enable 0 Interrupt disabled 1 Interrupt enabled M2_0_ECC_EN 0 M2 Block 0 ECC Error Enable 0 Interrupt disabled 1 Interrupt enabled GIR2 General Interrupt Register 2 Offset 0x54 Bit 31 30 29 28 27 26 25 24 SWT4 SWT3 SWT2 SWT1 SWT0 OCN_ERR Type R W Re...

Page 538: ...ECC 18 QUICC Engine module DRAM ECC Error Interrupt Reflects ECC error interrupt of the CE DRAM 0 Interrupt not asserted 1 Interrupt asserted TDM_P1ECC 17 TDM 4 7 Parity Error Interrupt Reflects parity error interrupt of TDM4 TDM5 TDM6 or TDM7 0 Interrupt not asserted 1 Interrupt asserted TDM_P0ECC 16 TDM 0 3 Parity Error Interrupt Reflects parity error interrupt of TDM0 TDM1 TDM2 or TDM3 0 Interr...

Page 539: ...rrupt 0 Interrupt not asserted 1 Interrupt asserted TDM0_TERR 1 TDM0 Transmit Error Interrupt Reflects TDM0 Transmit error interrupt 0 Interrupt not asserted 1 Interrupt asserted TDM0_RERR 0 TDM0 Receive Error Interrupt Reflects TDM0 Receive error interrupt 0 Interrupt not asserted 1 Interrupt asserted GIER2_0 General Interrupt Enable Register 2 for Cores 0 3 Offset 0x58 GIER2_1 Offset 0x5C GIER2_...

Page 540: ...nterrupt disabled 1 Interrupt enabled DDR_ERR_EN 22 DDR Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled DMA_ERR_EN 21 DMA Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 20 Reserved Write to zero for future compatibility CE_IECC_EN 19 ECC Error Interrupt of the CE IMEM Enable 0 Interrupt disabled 1 Interrupt enabled CE_DECC_EN 18 ECC Error Interrupt of the CE DRAM E...

Page 541: ...ERR_EN 4 TDM2 Receive Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM1_TERR_EN 3 TDM1 Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM1_RERR_EN 2 TDM1 Receive Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM0_TERR_EN 1 TDM0 Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled TDM0_RERR_EN 0 TDM0 Receive Error In...

Page 542: ...nterrupt Reflects L2 ICache initiator Class watchpoint interrupt 0 Interrupt not asserted 1 Interrupt asserted L2ICM_OV 7 L2 ICache Initiator CLASS Overrun Interrupt Reflects L2 ICache initiator Class overrun interrupt 0 Interrupt not asserted 1 Interrupt asserted CLS2_WP 6 CLASS2 Watchpoint Interrupt Reflects CLASS2 watchpoint interrupt 0 Interrupt not asserted 1 Interrupt asserted CLS2_OV 5 CLAS...

Page 543: ...t 7 6 5 4 3 2 1 0 L2ICM_OV_EN CLS2_WP_EN CLS2_OV_EN CLS1_ERR_EN CLS1_WP_EN CLS1_OV_EN CLS0_WP_EN CLS0_OV_EN Type R W Reset 0 0 0 0 0 0 0 0 Table 13 13 GIER2_ 0 3 Bit Descriptions Name Description Settings 31 30 Reserved Write to zero for future compatibility PM_EN 11 Performance Monitor Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled L2ICS_WP_EN 10 L2 ICache Target CLASS Watchpoint Inter...

Page 544: ...hpoint Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled CLS1_OV_EN 2 CLASS1 Overrun Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled CLS0_WP_EN 1 CLASS0 Watchpoint Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled CLS0_OV_EN 0 CLASS0 Overrun Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled Table 13 13 GIER2_ 0 3 Bit Descriptions Name Description Settings ...

Page 545: ...ls Full duplex operation allows the DMA controller to read data from one target and store it in its internal memory while concurrently writing another buffer to another target This capability can be used extensively when data is read from the M3 memory and written into the M2 memory The bidirectional DMA controller reads from one of the CLASS target ports while writing to the second one The DMA co...

Page 546: ...hannel parameter RAM PRAM is accessible to the DMA controller and the port interface and includes a parity mechanism Each channel has one dedicated PRAM line The external BD is fetched into the PRAM the first time the channel wins during arbitration When a buffer is activated the DMA controller generates a bus transaction with a maximum size as described in the buffer descriptor BTSZ field and dec...

Page 547: ...block is read from address 0x1000 The channel closes when the data transfer is complete and an interrupt is generated Burst transactions are used on the bus Table 14 1 Channel Parameter Values for a Simple Buffer BD BD Parameters Value Description 8 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x200 Size of transfer left for this buffer BD_BSIZE Buffer base size of cyclic buffer B...

Page 548: ...ead from address 0x1000 An interrupt is generated when the buffer size reaches zero and the transfer restarts from the base address 0x1000 Table 14 2 Channel Parameter Values for a Cyclic Buffer BD BD Parameters Value Description 8 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x200 Size of transfer left for this buffer BD_BSIZE 0x200 Buffer base size of cyclic buffer BD_ATTR SST 0...

Page 549: ...s 0x1000 buffer 0 When the buffer size is zero there is a jump to address 0x2000 buffer 1 0x200 byte blocks are read and an interrupt is generated Table 14 3 Channel Parameter Values for a Chained Buffer and a Simple Buffer BD BD Parameters Value Description 0 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x20 Size of transfer left for this buffer BD_BSIZE 0x20 Buffer base size of ...

Page 550: ...tal buffer BD0 Blocks of 0x100 bytes are read starting at address 0x1000 and an interrupt is generated every 0x100 bytes The mode is continuous and addressing is sequential Be aware that in an incremental buffer memory can be corrupted because of overwriting Table 14 4 Channel Parameter Values for an Incremental Buffer BD BD Parameters Value Description 0 BD_ADDR 0x1000 External memory buffer curr...

Page 551: ...0 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x200 Size of transfer left for this buffer BD_BSIZE 0x200 Buffer base size of cyclic buffer BD_ATTR CONT 0x1 Continuous mode Do not shut down the channel when size reaches zero CYC 0x1 Reinitialize BD_ADDRESS to original value when size reaches zero NBD 0x1 When size reaches zero next request calls buffer 1 BTSZ 0x7 Maximum transfer ...

Page 552: ...nt The parameters of the third and fourth dimensions must be set to zero Figure 14 7 shows an example of a two dimensional simple buffer Figure 14 7 Two Dimensional Simple Buffer Table 14 6 lists the configuration of a simple buffer designated as channel BD8 A 0x2000 0x80 0x40 byte two dimensional block is read from address 0x1000 The first dimension is a line of 0x40 bytes The second dimension is...

Page 553: ...BD_ADDR when the size reaches zero BTSZ 0x7 Maximum transfer size is one burst of 64 bytes BD 0x1 Buffer dimension is 2 SSTD 0x1 Interrupt issued at the end of the second dimension CONTD 0x0 Simple buffer BD_MD_2D M2D_COUNT 0x80 Second dimension iterations left M2D_BCOUNT Second dimension base number of iterations M2D_OFFSET 0x1C0 Second dimension offset between two consecutive iterations BD_MD_3D...

Page 554: ..._MD_ATTR BD 2 DMACHCR xMDC 1 The M2D_COUNT and M3D_COUNT must be set to each dimension parameter The M2D_OFFSET and M3D_OFFSET must be set to the next address offset for each dimension loop The MxD_OFFSET is written in two s complement The parameters of the fourth dimension must be cleared to zero Figure 14 8 shows a three dimensional simple buffer Figure 14 8 Three Dimensional Simple Buffer 0x100...

Page 555: ...ent Figure 14 9 shows an example four dimensional simple buffer Table 14 7 Channel Parameter Values for a Three Dimensional Simple Buffer BD BD Parameters Value Description 8 BD_ADDR 0x1000 External memory buffer current address BD_MD_SIZE 0x40 Size of transfer left for this buffer BD_MD_BSIZE 0x40 Buffer base size of continuous buffer BD_MD_ATTR SST 0x1 Generate interrupt when buffer ends CONT 0x...

Page 556: ...ffset between each 0x40 bytes transaction is 0xF3C0 The two dimensional buffers execute 0x100 times for each fourth dimension iteration The offset between each two dimensional buffers is 0xF3FB0 0x1090 0xF5040 The channel closes when the transfer completes after 0x80 iterations of the three dimensional buffer and an interrupt is generated Burst transactions are used on the bus 0x121000 Interrupt 0...

Page 557: ...x40 Size of transfer left for this buffer BD_MD_BSIZE 0x40 Buffer base size of continuous buffer BD_MD_ATTR SST 0x1 Generate interrupt when buffer ends CONT 0x0 Non continuous mode the channel closes when the size reaches zero CYC 0x0 Increment BD_ADDR when the size reaches zero BTSZ 0x7 Maximum transfer size is one burst of 64 bytes BD 0x3 Buffer dimension is 4 SSTD 0x3 Interrupt issued at the en...

Page 558: ...ta is out of the source or in the destination This operation prevents out of sequence transactions at the ports Table 14 9 shows the channel parameter values associated with a three dimensional chained buffer BD8 and a four dimensional simple buffer BD10 Interrupt 0x103FF 0x11000 0xF3C0 0x100000 0x11B0 0x1090 0x8FB0 0x8F70 0x8CF7840 0x8C03800 0x8C12C00 0x8CF7800 0x1000 0xFCFB0 0x121000 0x130400 0x...

Page 559: ...3D_BCOUNT Third dimension base number of iterations M3D_OFFSET 0x1200 Third dimension offset between two consecutive iterations BD_MD_4D M4D_COUNT 0 Fourth dimension iterations left M4D_OFFSET 0 Fourth dimension offset between two consecutive iterations 10 BD_ADDR 0x1000 External memory buffer current address BD_MD_SIZE 0x40 Size of transfer left for this buffer BD_MD_BSIZE 0x40 Buffer base size o...

Page 560: ...et between the base address and the last transaction address Figure 14 11 shows an example cyclic buffer Figure 14 11 Two Dimensional Cyclic Buffer Table 14 10 lists the configuration of a two dimensional cyclic buffer designated as channel BD8 in this example A 0x2000 0x80 0x40 byte two dimension block is read from address 0x1000 The first dimension is a line of 0x40 bytes The second dimension is...

Page 561: ...er left for this buffer BD_MD_BSIZE 0x40 Buffer base size of continuous buffer BD_MD_ATTR SST 0x0 Do not generate interrupt when buffer ends CYC 0x1 Cyclic two dimensional buffer the third dimension offset is used to restore the base address CONT 0x1 Continuous mode The buffer does not close when BD_MD_BSIZE and M2D_COUNT reach zero BTSZ 0x5 Basic transfer size is 16 bytes BD 0x1 Buffer dimension ...

Page 562: ..._MD_SIZE 0x40 Size of transfer left for this buffer BD_MD_BSIZE 0x40 Buffer base size of continuous buffer BD_MD_ATTR SST 0x1 Generate interrupt when buffer ends CONT 0x1 Non continuous mode the channel closes when the size reaches zero CYC 0x1 Cyclic three dimensions BTSZ 0x5 Basic transfer size is 16 bytes BD 0x2 Buffer dimension is 3 SSTD 0x2 Interrupt issued at the end of the third dimension C...

Page 563: ...l has credit for maximum consecutive grants according to BD_ATTR TSZ and BD_ATTR BTSZ If TSZ is greater than BTSZ bytes the channel wins consecutively in BTSZ byte portions until TSZ is reached The channel may stop requesting before it is continuously granted the maximum transfer size The channel keeps its priority until the address is aligned The channel priority is updated when the buffer or dim...

Page 564: ...n by the EDF logic Reset mode Reloads the counter Maskable interrupt for threshold deadline crossing when an active counter crosses the threshold Four optional clock sources for the counters and a DMA predivider Automatic channel priority group supporting DMA based on EDF algorithm The EDF sorts the channels into four priority groups according to their time to deadline value The arbitration betwee...

Page 565: ...pending register 14 3 2 2 Counter Control The EDF field in the source BD_ATTR of the channel defines the EDF logic behavior when source BD_SIZE reached zero 14 3 2 3 Clock Source to the Counters All the counters share the same clock source There are four clock sources 3 external to the DMA clock sources and the DMA clock divided by 16 14 4 Interrupts The DMA controller uses two types of interrupts...

Page 566: ...f zero Note In some cases in which a PRAM parity error occurs the BD size zero error may also be set For each error source a bit in the DMA Error Register DMAERR indicates the error source DMAERR also samples the first channel that caused the first bus error and the first channel that caused the first parity error 14 5 Profiling The DMA supports system level profiling via the Channel Profiled CHAP...

Page 567: ...MA EDF Time to Dead Line Registers 0 15 DMAEDFDL 0 15 page 14 30 DMA EDF Control Register DMAEDFCTRL page 14 31 DMA EDF Mask Register DMAEDFMR page 14 32 DMA EDF Mask Update Register DMAEDFMUR page 14 32 DMA EDF Status Register DMAEDFSTR page 14 34 DMA Mask Register DMAMR page 14 34 DMA Mask Update Register DMAMUR page 14 35 DMA Status Register DMASTR page 14 36 DMA Error Register DMAERR page 14 3...

Page 568: ...6 25 24 23 22 21 20 19 18 17 16 BDTPTR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDTPTR DESO Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 15 DMABDBRx Field Descriptions Bits Reset Description Setting 31 28 0 Reserved Write to zero for future compatibility BDTPTR 27 4 0 Buffer Descriptor Table Pointer Holds the 24 most significant bits out o...

Page 569: ...sk completes Never write a 0 to this bit when the channel is active You must use DMACHDR to disable the channel first before disabling the channel Disabling the channel does not reset its value immediately the value is reset only when there are no more open requests on the bus interface See also the DMA Channel Enable Register on page 14 28 and the DMA Channel Disable Register on page 14 28 Writte...

Page 570: ...in Arbitration To update this field while the channel is active use the DMA_RRPGUR register see page 14 40 Written by User DMA controller 000 Highest priority 011 Lowest priority 1xx Reserved 12 0 Reserved Write to zero for future compatibility DPO 11 0 Destination Port Optimize Specifies how the destination port is to be optimized Written by User 0 Optimize for destination port requests latency 1...

Page 571: ... Register Setting 31 3 0 Reserved Write to zero for future compatibility PSCB 2 0 Port 1 Slow Confirmation For debug the DMA supports slow confirmation for all transactions Written by User 0 Fast confirmation on port 1 when possible 1 Slow confirmation on port 1 PSCA 1 0 Port 0 Slow Confirmation For debug the DMA supports slow confirmation for all transactions Written by User 0 Fast confirmation o...

Page 572: ...nd any non serviced request is lost The DISx bit is reset by the DMA logic When the user writes either a 1 to DMACHDR DISx or a 0 to DMACHCRx ACTV the channel is shut down If more channel requests are pending on the bus interface the channel is not disabled The DMACHDR DISx and corresponding DMACHER ENx and CHCRx ACTV are all set until the pending channel transactions are closed When all transacti...

Page 573: ...esponding DMACHFR bits Sx and Dx The register allows simultaneous freezing of channels during normal operation Note The DMA channels do not freeze immediately therefore after a channel freeze is set the DMA controller can issue new transactions for the channel until its pipeline is cleared Note When the DMA channel becomes frozen data may be left in the FIFO 14 6 6 DMA Channel Defrost Register DMA...

Page 574: ...et 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 Table 14 18 DMAEDFTDL 0 15 Field Descriptions Bits Reset Write By Description Settings ENC 31 0 User ENC This field enable this counter The counter will start counting when a task is asserted and this field set Note Enabling and disabling the channels change the counters value Disabling channels stops the counting and enabling them reloads the counters with their...

Page 575: ...3 22 21 20 19 18 17 16 CLK_SRC Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLK_DIV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 14 19 DMAEDFCTRL Field Descriptions Bits Write by Description Setting 31 18 Reserved Write to zero for future compatibility CLK_SRC 17 16 User Clock Source There are four clock sources for the EDF counters 00 DMA clock ...

Page 576: ...e R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 20 DMAEDFMR Field Descriptions Bits Write by Description Setting 31 16 Reserved Write to zero for future compatibility M 15 0 15 0 User Masks 15 0 Each bit corresponds to an interrupt request bit in the D...

Page 577: ...w Channel Mask Value Stores the new value of DMAEDFMR MASK_CH2 0 Not masked 1 Masked EN2 16 User Enable Mask Unmask Updating When set updates DMAEDFMR MASK_CH2 according to NM3 When DMAEDFMR MASK_CH2 is updated the DMA controller clears this bit 0 Update occurred 1 Perform update MASK_CH1 15 10 User Channel Number Indicate the channel number of the DMAEDFMR to change 000000 001111 Channel number 0...

Page 578: ...DMAMR is cleared at reset and you can enable a channel interrupt request by setting the appropriate Dx bit DMAEDFSTR DMA EDF Status Register Offset 0x344 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 ...

Page 579: ... Written by User Always set 1 for channel interrupt for destination BD or end of channel NM3 25 0 New Channel Mask value The new value of DMAMR MASKCH3 DES3 Written by User 0 Unmask 1 Mask EN3 24 0 Enable MASK UNMASK Update Updates DMAMR MASK_CH3 DES3 according to NM3 Then the DMA controller clears this bit Written by User DMA controller MASKCH2 23 19 0 Channel Number The channel number to which D...

Page 580: ... 8 0 Enable MASK UNMASK Update Updates DMAMR MASKCH0 DES0 according to NM0 Then the DMA controller clears this bit Written by User DMA controller MASKCH0 7 3 0 Channel Number The channel number to which DMAMR should be changed Written by User 00000 01111 Channel number 1xxxx Reserved DES0 2 0 Channel Number Destination Destination channel number to which DMAMR should be changed Written by User Alw...

Page 581: ...ly the channel that caused the error is frozen DMAERR DMA Error Register Offset 0x370 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDSZ PACH PADEST PBCH PBDEST Type R R W R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAE PBE THV PRTYPPRTYF PRTYB PRTY PRTYCH PRTYD Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 24 DMAERR Description Bits Rese...

Page 582: ... cleared when all bits in DMACNTSTR are cleared 0 No deadline violation 1 Deadline violation PRTYP 11 0 Parity Error on PRAM Indicates that the parity error occurred in the PRAM 0 No error indication on the PRAM 1 PRAM parity error indication PRTYF 10 0 Parity Error on FIFOs Indicates that the parity error occurred in the FIFOs 0 No error indication in the FIFO s 1 FIFO s parity error indication P...

Page 583: ... Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 25 DMADESR Field Descriptions Bits Write By Description Settings 31 2 Reserved Write to zero for future compatibility EXT 1 DMA External DMA Debug Request Event Set when external debug event occurs 0 Normal operation 1 External DMA debug request DBG 0 DMA Debug Mode Status Set when the DMA is in full Debug mode 0 Normal operation 1 DMA in Debu...

Page 584: ...requests are profiled DMARRPGUR DMA Round Robin Priority Group Update Register Offset 0x37C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH NRRPG EN TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 27 DMARRPGUR Field Descriptions Bits Description Settings 31 10 Reserved Write to zero for future com...

Page 585: ...ated channel If set a bit associated with a channel indicates that the channel is still frozen Note The corresponding bits are cleared when a channel is activated DMACHASTR DMA Channel Active Status Register Offset 0x380 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A...

Page 586: ...BASE offset CHCR DMADESBDPT 16 DMACHCR DMDC 1 Offset is the decoded value of DMABDBR DESO The VCOP channel BDs are located in memory outside the VCOP Each channel has a BD table to hold the BDs for both source and destination buffers All BDs of all channels must be located in memory connected to MBus interface 0 Figure 14 14 shows the structure of one dimensional BD which is a 128 bit entry Figure...

Page 587: ...imension For details on BD address calculation Figure 14 16 Example BD Table with a Mixed Dimensional Structure The BDs are either one dimensional or multi dimensional One dimensional BDs are chained only to one dimensional BDs and multi dimensional BDs are chained only to multi dimensional BDs The types of source and destination BDs are defined in the DMACHCR see page 14 25 Table 14 28 lists the ...

Page 588: ...e the channel BD_ATTR 63 32 Buffer Attributes This 32 bit parameter describes the attributes of the channel handling this buffer The fields of the BD_ATTR parameter are described in Table 14 29 BD_BSIZE 31 0 Buffer Base Size Holds the base size of the buffer BD_ATTR Buffer Attributes Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SST CYC CONTNPRTNO_INC NBD Type R W Reset Undefined Bit 15 14 1...

Page 589: ... Counter This field is valid only when the arbitration is time based It characterizes the time based arbitration mechanism for continuous buffers when the buffer size reaches zero and applies only when switching buffers 00 Continuous Channel and counter continue working normally 01 Reserved 10 Reserved 11 Resets the channel counter PP 13 12 Port priority Define priority for this buffer The bus Int...

Page 590: ...ntains the base size for the buffer first dimension BD_MD_SIZE 207 192 First Dimension Buffer Size Holds the remaining size for the buffer first dimension This value is incremented by the transfer size each time the DMA controller issues a transaction until it reaches zero When BD_MD_SIZE reaches zero its value is restored to the value of BD_MD_BSIZE Note BD_MD_SIZE must not be programmed to zero ...

Page 591: ... zero and the last data transaction ends Setting this bit in the destination buffer issues a masked interrupt request See also the SSTD bit 0 Do not set status 1 Set status when the size of the dimension selected by SSTD reaches zero CYC 46 Cyclic Address Indicates the behavior of BD_MD_ADDR when BD dimension count reaches zero For details on cyclic buffers see Section 14 2 Buffer Types on page 14...

Page 592: ...rface sets the priority for this buffer You must map the priority at the system level 00 Priority 0 lowest 11 Priority 3 highest TSZ 27 24 Transfer Size Indicates the maximum transfer size that the DMA controller issues when a request is detected 0000 512 bytes 0001 1 byte 0010 2 bytes 0011 4 bytes 0100 8 bytes 0101 16 bytes 0110 32 bytes 0111 64 bytes 1000 128 bytes 1001 256 bytes 1010 512 bytes ...

Page 593: ...eeze Dimension When the selected dimension is processed the internal logic masks all channel requests and freezes the channel The host must defrost the channel for further service This field is valid only if FRZ is set in the BD_MD_ATTR 00 Mask and freeze channel when first dimension ends 01 Mask and freeze channel when second dimension ends 10 Mask and freeze channel when third dimension ends 11 ...

Page 594: ...n two s complement The offset is added to the BD_MD_ADDR each time BD_MD_SIZE reaches zero Table 14 33 BD_MD_3D Field Descriptions Bits Description M3D_COUNT 51 40 Third Dimension Current Count Decrements each time the BD_MD_SIZE and M2D_COUNT reach zero The field is reloaded with the M3D_BCOUNT each time it reaches zero Note If the buffer is three dimensional or more this field cannot be 0 M3D_BC...

Page 595: ...I controller uses a 32 bit multiplexed address data bus that can run at frequencies up to 66 MHz The interface provides address and data parity with error checking and reporting The interface provides for three physical address spaces 64 bit address memory 32 bit address I O and PCI configuration space The PCI controller functions as a peripheral device on the PCI bus referred to as agent mode Aft...

Page 596: ...arbiter and uses GNT to receive grants from the external arbiter PCI initiator mode is enabled by setting PCICCR BMST As the target the PCI controller acts as a bridge between the PCI bus and the MSC8144E interconnect The PCI can be programmed to transfer transactions initiated by the PCI initiator to any of the following M2 memory M3 memory DDR memory or the configuration registers CCSR PCI targe...

Page 597: ...0000 A read implicitly addressed to the system interrupt controller The size of the vector to be returned is indicated on the byte enables after the address phrase Yes No Special cycle 0b0001 Provides a simple message broadcast mechanism Yes No I O read 0b0010 Accesses agents mapped in I O address space Yes No I O write 0b0011 Accesses agents mapped in I O address space Yes No 0b010x Reserved No r...

Page 598: ... PCI_TRDY or PCI_STOP it does not change PCI_DEVSEL PCI_TRDY or PCI_STOP until the current data phase completes When the VCOP as an initiator intends to complete only one more data transfer PCI_FRAME is deasserted and PCI_IRDY is asserted or kept asserted indicating the initiator is ready After the target indicates it is ready PCI_TRDY asserted the bus returns to the idle state 15 1 4 Addressing T...

Page 599: ...r PCI_TRDY asserted The exception to this is a target abort see Section 15 1 8 2 for more information As an initiator if the VCOP does not see the assertion of PCI_DEVSEL within 4 clocks of PCI_FRAME it terminates the transaction with an initiator abort as described in Section 15 1 8 2 15 1 6 Byte Enable Signals The byte enable signals BE 3 0 indicate which byte lanes carry valid data The byte ena...

Page 600: ...presents a turnaround cycle 15 1 8 1 Read and Write Transactions Both read and write transactions begin with an address phase followed by a data phase The address phase occurs when PCI_FRAME is asserted for the first time and the AD 31 0 signals contain a byte address and the PCI_C BE 3 0 signals contain a bus command The data phase consists of the actual data transfer and possible wait cycles the...

Page 601: ...s when data is transferred which occurs when both PCI_IRDY and PCI_TRDY are asserted on the same clock edge When either is deasserted a wait cycle is inserted and no data is transferred To indicate the last data phase PCI_IRDY must be asserted when PCI_FRAME is deasserted A write transaction starts when PCI_FRAME is asserted for the first time and the PCI_C BE 3 0 signals indicate a write command ...

Page 602: ...he assertion of PCI_FRAME it deasserts PCI_FRAME and then on the next clock deasserts PCI_IRDY On aborted reads the VCOP returns 0xFFFF_FFFF The data is lost on aborted writes When the VCOP as a target needs to suspend a transaction it asserts PCI_STOP Once asserted PCI_STOP remains asserted until PCI_FRAME is deasserted Depending on the circumstances data may or may not be transferred during the ...

Page 603: ...e elapsed between data phases This is a latency disconnect see Figure 15 5 AD 1 0 is 0bx1 a reserved burst ordering encoding during the address phase and one data phase has completed The PCI command is a configuration command and one data phase has completed A streaming transaction crosses a 4K page boundary A streaming transaction runs out of I O sequencer buffer entries A cache line wrap transac...

Page 604: ...d target of a transaction and an address parity error occurs or a data parity error occurs on a write transaction to system memory it continues the transaction on the PCI bus but aborts internally The VCOP does not target abort in this case If the VCOP is initiating a transaction and the transaction terminates with a target abort undefined data will be returned on a read and write data will be los...

Page 605: ...chieved by performing speculative reads from memory in prefetchable space A block of memory may be marked as prefetchable by setting the PCI configuration registers bit for the inbound address translation see page 15 42 for details in the following cases When reads do not alter the contents of memory reads have no side effects When reads return all bytes regardless of the byte enable signals When ...

Page 606: ...an initiator abort In the special cycle case the received initiator abort bit in the configuration status register is not set The address phase contains no valid information other than the command field Even though there is no explicit address the address data lines are driven to a stable state and parity is generated During the data phase the address data lines contain the message type and an opt...

Page 607: ... 4 Error Functions This section discusses PCI bus errors 15 1 8 4 1 Parity During valid 32 bit address and data transfers parity covers all 32 address data lines and the 4 command byte enable lines regardless of whether or not all lines carry meaningful information Byte lanes not actually transferring data are driven with stable albeit meaningless data and are included in the parity calculation Du...

Page 608: ... write to system memory Figure 15 6 shows the possible assertion points for PCI_PERR if the VCOP detects a data parity error Figure 15 6 PCI Parity Operation As an initiator the VCOP attempts to complete the transaction on the PCI bus if a data parity error is detected and sets the data parity reported bit in the configuration space status register If a data parity error occurs on a read transacti...

Page 609: ... an interrupt is also asserted to the core as an option 15 1 8 5 PCI Inbound Address Translation For inbound transactions transactions generated by an external initiator on the PCI bus where the VCOP responds as a target device the VCOP only responds to PCI addresses within the windows mapped by the PCI inbound base address registers PIBARs or PIMMR base address register PIMMBACR If there is an ad...

Page 610: ...Configuration Access Registers Otherwise if the address hits any of the outbound translation windows the transaction is forwarded to PCI port Note Do not attempt to access the PCI Outbound Window until the PCICCR BMST bit is set See Section 15 2 2 3 PCI Command Configuration Register PCICCR on page 15 23 for details about the BMST bit Outbound address translation is provided to allow the outbound ...

Page 611: ...t overlap However outbound translation destination windows can be overlapped 15 1 8 7 Transaction Ordering The following rules are applied to maintain proper ordering of transactions An Outbound read transaction from the internal memory pulls out of the PCI any posted Inbound writes that originated on the PCI port and were posted before the read data arrives from the PCI The PCI is always able to ...

Page 612: ...ister CONFIG_DATA see page 15 21 PCI Interrupt Acknowledge Register PCI_INT_ACK see page 15 22 Note The PCI configuration access registers use a base address of 0xE7FFFFF0 The PCI configuration space registers are defined by the PCI specification These registers are accessed by PCI initiators using configuration accesses or by a local initiator using PCI configuration access registers The PCI conf...

Page 613: ...unctions general control and status and address translation control for the inbound and outbound paths They can be accessed by PCI initiators via the VCOP to the internal memory interface via the PIMMR inbound window The PCI memory mapped registers include PCI Error Status Register PCI_ESR see page 15 34 PCI Error Capture Disable Register PCI_ECDR see page 15 35 PCI Error Enable Register PCI_EER s...

Page 614: ...of the CONFIG_ADDRESS register CONFIG_ADDRESS PCI Configuration Address Register Offset 0x0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN BN Type W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DN FN RN Type W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 3 CONFIG_ADDRESS Field Descriptions Bits Description Settings EN 31 Enable Configuration Transaction...

Page 615: ...nternal configuration space enabled 111 Special cycles and interrupt acknowledge transactions enabled All other values are invalid RN 7 2 Register Number This field selects a 4 byte word in the PCI controller internal configuration space 1 0 Reserved Write to 0 for future compatibility CONFIG_DATA PCI Configuration Data Register Offset 0x4 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CFG_DA...

Page 616: ...ined PCI configuration space 15 2 2 1 Vendor ID Configuration Register VIDCR Table 15 6 shows the bit settings of the VIDCR PCI_INT_ACK PCI Interrupt Acknowledge Register Offset 0x8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCI_INT_ACK Type R Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI_INT_ACK Type R Reset x x x x x x x x x x x x x x x x x undefine...

Page 617: ...t 15 14 13 12 11 10 9 8 FB B SERREN Type R R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PERRR MWI SC BMST MEM IO Type R R W R R R R W R W R Reset 0 0 0 0 0 0 0 0 Table 15 7 PCICCR Field Descriptions Bits Description Settings 15 10 Reserved Write to 0 for future compatibility FB B 9 Fast Back to Back Hard wired to 0 SERREN 8 SERR Enable The enable bit for the SERR driver Address parity errors are ...

Page 618: ...to memory space accesses 0 PCI controller does not respond to memory space accesses 1 As a target the PCI controller responds to memory space accesses IO 0 I O Hard wired to 0 PCISCR PCI Status Configuration Register Offset 0x06 Bit 15 14 13 12 11 10 9 8 DPERR SSERR RMA RTA STA DEVSEL_T DPD Type R W R R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FB BC 66M CL Type R Reset 1 0 1 0 0 0 0 0 Table 15 ...

Page 619: ...rget abort to a PCI initiator 0 No parity error 1 Parity error detected DEVSEL_T 10 9 DEVSEL Timing Hard wired to 00 DPD 8 Initiator Data Parity Error This bit is set when a data parity error is detected on the PCI bus if the VCOP is the initiator that initiated the transaction and bit 6 in the PCI command register is set 0 No parity error 1 Parity error detected FB BC 7 Fast Back to Back Capable ...

Page 620: ...he class code Table 15 12 shows the bit settings of the BCCCR SPICR Standard Programming Interface Configuration Register Offset 0x09 Bit 7 6 5 4 3 2 1 0 PI Type R Reset 0 0 0 0 0 0 0 0 Table 15 10 SPICR Field Descriptions Bits Description PI 7 0 Programming Interface This field is hard wired internally as 0x00 SCCR Subclass Code Configuration Register Offset 0x0A Bit 7 6 5 4 3 2 1 0 SC Type R Res...

Page 621: ...ptions Bits Description CLS 7 0 Cache Line Size This field represents the cache line size of the system in terms of 32 bit words Although the register is writable only the value 0x08 is legal LTCR Latency Timer Configuration Register Offset 0x0D Bit 7 6 5 4 3 2 1 0 LT Type R W R Reset 0 0 0 0 0 0 0 0 Table 15 14 LTCR Field Descriptions Bits Description LT 7 3 Latency Timer This field specifies wit...

Page 622: ...r Type Configuration Register Offset 0x0E Bit 7 6 5 4 3 2 1 0 HT Type R Reset 0 0 0 0 0 0 0 0 BISTCCR BIST Control Configuration Register Offset 0x0F Bit 7 6 5 4 3 2 1 0 BIST_CTL Type R Reset 0 0 0 0 0 0 0 0 PIMMRBACR PIMMR Base Address Configuration Register Offset 0x10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ...

Page 623: ...Offset 0x14 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA PRE T MSI Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 16 GPLBAR0 Field Descriptions Bits Description BA 31 12 Base Address This field defines the low portion of the base address for the inbound window 11 4 Reserved Write to 0 f...

Page 624: ...write to a GPL extended base address register also causes a change in the base address bits that are not masked according to the IWS field of PIWAR 1 2 in the corresponding PIBAR 1 2 PIEBAR 1 2 Note that this write operation does not change the bits that are masked by the IWS field For read operations these masked bits always return zeros Table 15 18 shows the GPLEXTBAR 1 2 bit field Table 15 17 G...

Page 625: ...ound window SVIDCR Sub System Vendor ID Configuration Register Offset 0x2C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVID Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 19 SVIDCR Field Descriptions Bits Description Settings SVID 15 0 Sub System Vendor ID This field identifies the board or sub system that contains this device SDIDCR Sub System Device ID Configuration Register Offset 0x2E B...

Page 626: ...abilities Pointer Configuration Register Offset 0x34 Bit 7 6 5 4 3 2 1 0 CAP_PTR Type R Reset 0 0 0 0 0 0 0 0 INTLINCR Interrupt Line Configuration Register Offset 0x3C Bit 7 6 5 4 3 2 1 0 INT_PIN Type R W Reset 0 0 0 0 0 0 0 0 Table 15 21 INTLINCR Field Descriptions Bits Description Settings IL 7 0 Interrupt Line This value is used to communicate interrupt line routing information The value has n...

Page 627: ...44 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSD CFG_ LOCK TLTD MLTD Type R W Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Table 15 23 PCIFCR Field Descriptions Bits Description Settings 15 11 Reserved Write to 0 for future compatibility MSD 10 Master Streaming Disable This bit can prevent the PCI from streaming as an initiator 0 Streaming is enabled when operating as an initiator 1 Streaming is disabled...

Page 628: ...Disable This bit determines whether the VCOP while acting as a PCI initiator terminates a transaction upon the expiration of the initiator latency timer 0 Initiator latency timer enabled 1 Initiator latency timer disabled 0 Reserved Write to 0 for future compatibility PCI_ESR PCI Error Status Register Offset 0x000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MERR Type R W Reset 0 0 0 0 0 0 ...

Page 629: ...get of a transaction and the PCI_PERR input signal is asserted on a read access or a data parity error is detected by this VCOP on a write access 0 No error 1 Error detected NORSP 6 No Response This bit is set when there is no response to a transaction initiated by this VCOP on the PCI bus no PCI_DEVSEL assertion 0 Normal transaction response 1 No response TABT 5 Target Abort This bit is set when ...

Page 630: ...capture for a target abort error 0 Capture is enabled 1 Capture is disabled 4 0 Reserved Write to 0 for future compatibility PCI_EER PCI Error Enable Register Offset 0x008 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 APAR PCI SERR MP ERR TP ERR NO RSP TABT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 631: ...rved Write to 0 for future compatibility PCI_EATCR PCI Error Attributes Capture Register Offset 0x00C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ERRTYPE BN TS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD BE PB VI Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 27 PCI_EATCR Field Descriptions Bits Description Settings 31 Reserved Writ...

Page 632: ...lewords in the cache line on which the error occurred This field is valid only if the VCOP was the initiator of the transaction 00 4 double words 01 1 double word 10 2 double words 11 3 double words 19 16 Reserved Write to 0 for future compatibility CMD 15 12 PCI Command This field contains the PCI command PCI_C BE 3 0 of the transaction 11 8 Reserved Write to 0 for future compatibility BE 7 4 PCI...

Page 633: ... 16 PCI_EA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI_EA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 28 PCI_EACR Field Descriptions Bits Description PCI_EA 31 0 PCI Error Address Contains the low portion of the address associated with the first detected error PCI_EEACR PCI Error Extended Address Capture Register Offset 0x014 Bit 31 30 2...

Page 634: ...0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI_EDR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 30 PCI_EDLCR Field Descriptions Bits Description PCI_EDR 31 0 PCI Error Data Contains the data associated with the first detected error PITAR0 PCI Inbound Translation Address Registers 0 2 Offset 0x068 PITAR1 Offset 0x050 PITAR2 Offset 0x038 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 635: ...s the PIEBAR 1 2 bit fields PIBAR0 PCI Inbound Base Address Registers 0 2 Offset 0x070 PIBAR1 Offset 0x058 PIBAR2 Offset 0x040 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 32 PIBAR 0 2 Field Descriptions Bits Description BA 31 0 Base Address ...

Page 636: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 34 PIWAR 0 2 Field Descriptions Bits Description Settings EN 31 Enable This bit enables the address translation window PCI addresses that match the definition of the window will be recognized by the VCOP and translated to the local memory space 0 Address translation is disabled for this window 1 Address translation is enabled for this window 30 Reserved Writ...

Page 637: ...et 0x118 POTAR2 Offset 0x130 POTAR3 Offset 0x148 POTAR4 Offset 0x160 POTAR5 Offset 0x178 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 35 POTAR 0 5 Field Descriptions Bits Description 31 20 Reserved Write to 0 for future compatibility TA 19 0 ...

Page 638: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 36 POBAR 0 5 Field Descriptions Bits Description 31 20 Reserved Write to 0 for future compatibility BA 19 0 Base Address This field contains the starting address of the outbound translated window This 20 bit field corresponds to bits 31 12 of a 32 bit address PO...

Page 639: ... bit is set the PCI controller may combine consecutive cache line transfers into one PCI transaction 0 Streaming disabled 1 Streaming enabled 28 20 Reserved Write to 0 for future compatibility CM 20 0 Comparison Mask This field contains the size of the translation window The bits that are 1 in this field indicate bits of the transaction address that should be matched to the value in the PCI outbou...

Page 640: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN PTV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 39 DTCR Field Descriptions Bits Description Settings EN 31 Enable This bit enables the discard timer 0 Disabled 1 Enabled 30 24 Reserved Write to 0 for future compatibility PTV 23 0 Preload Timer...

Page 641: ...d packets are transported from the MSC8144E device back to the host The Serial RapidIO controller directs the traffic flow between the MSC8144E and any other RapidIO device through the RMU for messages and doorbells and through the RapidIO DMA channels for NWRITEs NWRITE_Rs NREADs and SWRITEs The host and the MSC8144E communicate as follows The host sends messages to the destination MSC8144E devic...

Page 642: ...ansport information field 34 bit addressing Up to 256 byte data payload Up to eight outstanding unacknowledged RapidIO transactions Hardware recovery only All transaction flows and all priorities Register and register bit extensions as described in the RapidIO Interconnect Specification Revision 1 2 Part VIII Error Management Extensions Specification Packet types as defined in the RapidIO Intercon...

Page 643: ...ification Revision 1 2 Two outbound message controllers Two inbound message controllers One outbound doorbell controller One inbound doorbell controller One inbound port write controller The RMU incorporates the following general features of the RapidIO specification Small or large size transport information field All transaction flows and all priorities Register and register bit extensions as des...

Page 644: ...nterfaces Transmission rates of 1 25 2 5 and 3 125 Gbaud data rates of 1 0 2 0 and 2 5 Gbps respectively Auto detection of 1x and 4x mode operation during port initialization Error detection for packets and control symbols Link initialization synchronization error recovery and time out RapidIO endpoint does not support the following features of RapidIO 1x 4x operation RapidIO endpoint cannot be co...

Page 645: ...teristics refer to the RapidIO Interconnect Specification Revision 1 2 16 2 RapidIO Interface Basics This section summarizes the RapidIO transactions packet format and control symbols It also discusses how the configuration registers are accessed via the RapidIO packets and the operation of the ATMU translation windows for translating RapidIO addresses to local physical addresses and vice versa Ta...

Page 646: ...te with response SWRITE 0110 N A Streaming Write MAINT read 1000 0000 Maintenance read MAINT write 0001 Maintenance write MAINT read response 0010 0000 Done maintenance read response 0111 Error response MAINT write response 0011 0000 Done maintenance write response 0111 Error response MAINT port write 0100 NA Maintenance port write1 RESPONSE without data 1101 0000 0000 I O done response 0111 I O e...

Page 647: ...siz e src TID addr wd ptr x a m b s dword 0 dword n NWRITE ackID rsv 0 prio tt ftype dest ID src ID tty pe wrsiz e don t care addr wd ptr x a m b s dword 0 dword n SWRITE ackID rsv 0 prio tt ftype dest ID src ID addr 29 rsv 1 0 xambs 2 dword 0 dword n MAINT read ackID rsv 0 prio tt ftype dest ID src ID tty pe rd wr size src TID hop cnt cfg offset wd ptr rs v 0 NA MAINT write ackID rsv 0 prio tt ft...

Page 648: ...ftype dest ID src ID tty pe status tar TID dword 0 dword n DOORBELL ackID rsv 0 prio tt ftype des tID src ID rsv 0 src TID Info msb Info lsb NA MESSAGE ackID rsv 0 prio tt ftype dest ID src ID msglen 4 ssize 4 letter 2 mbox 2 msgseg 4 dword 0 dword n Table 16 5 1x 4x LP Serial Control Symbol Format Bits Description 24 stype0 param0 param1 stype1 cmd CRC 3 5 5 3 3 5 000 pkt_ackID buf_stat crc Packe...

Page 649: ...xpecting ackID 2 00011 Expecting ackID 3 00100 Expecting ackID 4 00010 Expecting ackID 5 00110 Expecting ackID 6 00111 Expecting ackID 7 port_stat 00010 Error unrecoverable 00100 Retry stopped 00101 Error stopped 10000 OK 000 000 crc Start of packet 001 000 crc Stomp 010 000 crc End of packet 011 000 crc Restart from retry 100 cmd crc Link request cmd 011 Reset the receiving device 100 Return inpu...

Page 650: ... second method is based on RapidIO MAINT requests This method allows an external device limited access to local RapidIO configuration register space Any maintenance access beyond the first 64 KB of RapidIO configuration register space is denied lower 64 KB contains RapidIO architecture registers upper 64 KB contains RapidIO implementation registers A 32 bit data payload of all zeros is returned fo...

Page 651: ...ysical address offset is a RapidIO port common value and is provided by the system configuration input RapidIO_config_addr_offset 0 4 The RapidIO address translation is as follows addr 0 32 CCSRBAR 0 15 0b00000000000000000 0b0000 0b0000000000 rapidio_config_addr_offset 0 4 10b0000 0b0000 0b0000000000000000 config_offset 8 20 addr 0 32 CCSRBAR 0 15 0b00000000000000000 0b0000 0b0000000000 rapidio_co...

Page 652: ...er set hit For both inbound and outbound translation the smallest window size is 4 K and the largest window size is 16 G for inbound translation and 64 G for outbound translation The default window register set causes no translation of the transaction address for inbound transactions because the RapidIO address space has 34 bits and the internal interconnect address space has 36 bits For outbound ...

Page 653: ...nted windows achieving the equivalent behavior would require multiple windows Figure 16 2 shows an example of this capability A window is defined to be 4 Kbyte in size and is defined to have 4 segments and no subsegments Each segment is assigned to target deviceID 0x05 and each segment is given a different write transaction type attribute segment 0 is assigned NWRITE segment 1 is assigned SWRITE s...

Page 654: ...ss bits 22 29 The generated NWRITE transaction has the same target device offset as the write to segment 0 but is instead targeted to deviceID 9 Combinations of aliasing and multi targeting are also possible for a window 16 2 5 2 Outbound Windows RapidIO Endpoint implements nine outbound ATMU translation windows for translating local physical address to RapidIO address Port n RapidIO Outbound Wind...

Page 655: ...in the RapidIO request packet format RapidIO address is a 31 bit double word physical address or 34 bit byte address Internal address 0 32 is a 33 bit double word physical address or 36 bit byte address The ATMU window hit definition and RapidIO address translation are as follows 1 4K window size smallest window size A window hit is defined as BEXADD 0 3 BADD 0 19 matching internal address 0 23 Ra...

Page 656: ...o generate different transactions types allow a single ATMU window to generate multiple RapidIO target IDs Table 16 6 lists the various combination options Table 16 6 Outbound ATMU Window Segments Number of Segments NSEG Number of Sub Segments NSSEG Transaction Type Given by the Segment Register Target ID Given by Segment Register or elsewhere Comments 0 0 01 02 Non segmented window 2 0 01 1 02 Se...

Page 657: ...to cross window boundaries Although not a practical programming application the RapidIO endpoint handles this as follows 1 If a request hits base address match an ATMU window 1 8 and the transaction end address extends into another ATMU window with lower priority but is still contained within the boundary of the hit window the translation window is the hit window 2 If a request hits base address m...

Page 658: ...gher priority window is programmed to lie entirely within a lower priority window then it is possible for a transaction to cross window boundaries The RapidIO endpoint handles this as follows 1 If a request hits base address match an ATMU window 1 8 default and the transaction end address extends into another ATMU window with higher priority an Figure 16 5 Valid Hit that Extends Beyond the Window ...

Page 659: ...MU window 1 8 and the transaction end address exceeds the size of the window an outbound ATMU crossed boundary error is generated and logged The outbound request is discarded Figure 16 6 Boundary Crossing Error Due to Extension Into a Higher Priority Window Figure 16 7 Boundary Crossing Error Due to Extension Beyond the Higher Priority Window Boundary Figure 16 8 Boundary Crossing Error Due to Tra...

Page 660: ...dpoint implementation allows up to a 34 bit 0 33 RapidIO address and a 36 bit 0 35 internal addressing The MSC8144 device is confined to 32 bit addresses so the top 4 bits 0 3 of the inbound translation address should be set to all 0s Other settings result in undefined behavior An external processor should not assume that a write to any ATMU register is complete until a response is received Table ...

Page 661: ...RapidIO address 21 30 16 KB window size A window hit is defined as BEXADD 0 1 BADD 0 17 matching RapidIO address 0 19 Internal interconnection addr 0 32 TREXAD 0 3 TRAD 0 17 RapidIO address 20 30 Window sizes 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB 256 MB 512 MB 1GB 2 GB are not shown 4 GB window size A window hit is defined as BEXADD 0 1 matching RapidIO addr...

Page 662: ... it is possible for a transaction to cross window boundaries The RapidIO endpoint handles this situation as follows If a request hits base address match an ATMU window 1 4 default and the transaction end address extends into another ATMU window with a higher priority an ATMU crossed boundary error is generated and logged If a request hits multiple ATMU windows 1 4 default and the transaction end a...

Page 663: ...ysical Configuration Register and clear all errors 4 Disable the input port receiver IPD bit 1 in the Port n Control Command and Status Register This will allow the four consecutive link request reset device control symbols to be generated with only idle control symbols between the link request reset device control symbols 5 Generate four link request reset device control symbol using the Port n L...

Page 664: ...llows them be transferred if the port is initialized Drain mode due to Failed Threshold does not cause any packet acknowledgements to be dropped If a discarded packet in the outgoing data stream requires a logical response a packet response time out will occur if the packet response timer is enabled PRTOCCSR is non 0 16 2 8 Input Port Disable Mode When PnCCSR PD is set the RapidIO port is placed i...

Page 665: ...tanding and the ackIDs is already lined up then the write actually causes the ackIDs not to match and the link is not recovered 5 Software should cause the link partner to send a link request input status to ensure that the RapidIO inbound port is operating normally 6 Software clears the Failed Encountered bit or the Output Buffer Drain Enable bit whichever one caused the Drain mode thus clearing ...

Page 666: ...to the interrupt is not crucial to port performance The port is still functional When a notification error is detected the appropriate bit is set in the error specific register an interrupt is generated and in some cases the error is captured In all cases the RapidIO port continues operating Notification errors are detected in both the physical and logical layers Fatal errors There are two types o...

Page 667: ...abled The Cause Field column indicates which cause field is used with the associated packet not accept control symbol for input error recovery The EME Error Enable Detect column indicates which bit of the P0ERECSR see page 16 137 allows the error to increment the error rate counter and lock the Port 0 Error Capture registers and also which P0EDCSR bit is set when the error is detected see page 16 ...

Page 668: ...l character Enter input error stopped Enter output error stopped 5 Received invalid illegal character 1c Received a packet with embedded idles Enter input error stopped 5 Received invalid illegal character 1d Received a control symbol with a bad CRC P0PCR CCC enables detect Enter input error stopped Enter output error stopped 2 Received a control symbol with bad CRC Received corrupt control symbol...

Page 669: ...d ACK control symbol Enter output error stopped Received packet not a ccepted symbol PNA 2b Received an ACK accepted or retry control symbol when there are no outstanding packets Enter output error stopped Unsolicited ACK symbol UCS 2b Received packet ACK accepted for a packet whose transmission has not finished Enter output error stopped 2b Received a Link response control symbol when no outstand...

Page 670: ...cal RapidIO Threshold Response Error Error Enable RapidIO Endpoint Action EME Error Type Error Detect Interrupt Clear Notification Errors Error rate counter exceeded the degraded threshold P0ERTCSR ERDTT 0 and any bit in P0EECSR enables detect and interrupt generation Generate interrupt Continue to operate normally Degraded threshold P0ESCSR ODE Write 1 to P0ESCSR ODE Fatal Errors Consecutive retr...

Page 671: ...is false Yes if LTLEECSR ITTE is set LTLEDCSR ITTE Yes SourceID Not Checked for error TransactionType Received RapidIO packet with reserved TType for this ftype Yes if LTLEECSR ITD is set LTLEDCSR ITD Yes RdSize Not checked for error SrcTID Not checked for error Address WdPtr Xambs Read request hits overlapping ATMU windows Refer to Section 16 2 5 4 2 Window Boundary Crossing Errors on page 16 22 ...

Page 672: ... 11 Hardware Errors For Maintenance READ WRITE Request Transaction Error Interrupt Status Bit Set Error Response Comments Priority Priority of maintenance read or write request transaction is 3 Yes if LTLEECSR ITD is set LTLEDCSR ITD No RapidIO packet is dropped TransportType Received reserved TT Yes LTLEDCSR TSE No RapidIO packet is dropped Received TT that is not enabled Error is valid when pass...

Page 673: ...d on page 16 133 uses the incoming RapidIO packet for a small transport packet as follows LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLDIDCCSR DIDMSB gets 0s LTLDIDCCSR DID gets packet bits 16 23 LTLDIDCCSR SIDMSB gets 0s LTLDIDCCSR SID gets packet bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s The Logical Transport L...

Page 674: ...ith reserved TType for this ftype Packet is treated as Nwrite Transaction Yes if LTLEECSR ITD is set LTLEDCSR ITD Yes for NWRITE_R No for NWRITE RapidIOpacket is dropped WrSize Not unsupported transaction WrSize request is for one of reserved sizes Yes if LTLEECSR ITD is set LTLEDCSR ITD Yes for NWRITE_R No for NWRITE RapidIOpacket is dropped for NWRITE Address WdPtr Xambs Not unsupported transact...

Page 675: ...r Address Capture Command and Status Register uses the incoming RapidIO packet for a small transport packet as follows LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLDIDCCSR DIDMSB gets 0s LTLDIDCCSR DID gets packet bits 16 23 LTLDIDCCSR SIDMSB gets 0s LTLDIDCCSR SID gets packet bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI ge...

Page 676: ...SR TSE is set LTLEDCSR TSE No RapidIO packet is dropped DestID DestID does not match this port DeviceID if Alternate DeviceID is disabled or DestId does not match either Alternate DeviceID or DeviceId if Alternate DeviceID is enabled Error is valid when passthrough accept_all is false Yes if LTLEECSR ITTE is set LTLEDCSR ITTE No RapidIO packet is dropped SourceID Not checked for error Address WdPt...

Page 677: ...SR SIDMSB gets 0s LTLDIDCCSR SID gets packet bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s The Logical Transport Layer Address Capture Command and Status Register uses the incoming RapidIO packet for a large transport packet as follows LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 46 76 LTLDIDCCSR DIDMSB gets packet bits 16 23...

Page 678: ...d and ignored Transaction Type Not unsupported transaction Received RapidIO packet with reserved TType for the FType Yes if LTLEECSR TD is set LTLEDCSR TD No RapidIO packet is dropped and ignored Not unsupported response Maintenance read write response does not correspond to an outstanding valid message read write request Yes if LTLEECSR TD is set LTLEDCSR TD No RapidIO packet is dropped and ignor...

Page 679: ...nsport packet as follows LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLDIDCCSR DIDMSB gets 0s LTLDIDCCSR DID gets packet bits 16 23 LTLDIDCCSR SIDMSB gets 0s LTLDIDCCSR SID gets packet bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s The Logical Transport Layer Address Capture Command and Status Register uses the incomin...

Page 680: ...disabled or DestId does not match either Alternate DeviceID or DeviceId if Alternate DeviceID is enabled Error valid when passthrough accept_all is false Yes if LTLEECSR ITTE is set LTLEDCSR ITTE Yes if priority is not 3 Else packet is dropped If priority is 3 packet is dropped SourceID Not checked for error MsgLen Ssize Ltr Mbox MsgSeg Not checked for error PayloadSize Message payload size is lar...

Page 681: ...IDCCSR SIDMSB gets 0s LTLDIDCCSR SID gets bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s The Logical Transport Layer Address Capture Command and Status Register uses the incoming RapidIO packet for a large transport packet as follows LTLACCSR XA gets packet bits 94 95 LTLACCSR A gets packet bits 64 92 LTLTLTLDIDCCSR DIDMSB gets packet bits 16 2...

Page 682: ...for error Other Received message response with SOCAR M disabled Yes if LTLEECSR UR is set LTLEDCSR UR No RapidIO packet is dropped and ignored The Logical Transport Layer Address Capture Command and Status Register uses the incoming RapidIO packet for a small transport packet as follows LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLTLTLDIDCCSR DIDMSB gets 0s LTLDIDCCSR DI...

Page 683: ... Not checked for error Other Received doorbell request with DOCAR D disabled Yes if LTLEECSR UT is set LTLEDCSR UT Yes if priority is not 3 Else packet is dropped The Logical Transport Layer Address Capture Command and Status Register uses the incoming RapidIO packet for a small transport packet as follows LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLTLTLDIDCCSR DIDMSB g...

Page 684: ...e DeviceID or DeviceId if Alternate DeviceID is enabled Error is valid when passthrough accept_all is false Yes if LTLEECSR ITTE is set LTLEDCSR ITTE No RapidIO packet is dropped and ignored SourceID Does not match the request s DestID Yes if LTLEECSR UR is set LTLEDCSR UR No RapidIO packet is dropped and ignored Status Not UR or UT Not one of Done Error Retry Yes if LTLEECSR ITD is set LTLEDCSR I...

Page 685: ...bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s The Logical Transport Layer Address Capture Command and Status Register uses the incoming RapidIO packet for a large transport packet as follows for all entries but the last one in which the capture registers are loaded from original request RapidIO packet LTLACCSR XA gets packet bits 94 95 LTLACCSR A gets packet bits 64 92 LTLTLTLD...

Page 686: ...abled or DestId does not match either Alternate DeviceID or DeviceId if Alternate DeviceID is enabled Error valid when passthrough accept_all is false Yes if LTLEECSR ITTE is set LTLEDCSR ITTE No RapidIO packet is dropped SourceID Not checked for error TransactionType Not checked for error WrSize Not UT Is one of reserved sizes or less than 4 bytes Yes if LTLEECSR ITD is set LTLEDCSR ITD No RapidI...

Page 687: ...SR SID gets bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s In Table 16 19 the Logical Transport Layer Address Capture Command and Status Register uses the incoming RapidIO packet for a large transport packet as follows for all entries but the blank ones LTLACCSR XA gets packet bits 94 95 LTLACCSR A gets packet bits 64 92 LTLTLTLDIDCCSR DIDMSB g...

Page 688: ...ress Capture Command and Status Register uses the original RapidIO packet sent out by outbound For a small transport packet it uses the following LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLTLTLDIDCCSR DIDMSB gets 0s LTLDIDCCSR DID gets packet bits 16 23 LTLDIDCCSR SIDMSB gets 0s LTLDIDCCSR SID gets bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet b...

Page 689: ...t attempted to send outbound For a small transport packet it uses the following LTLACCSR XA gets packet bits 78 79 LTLACCSR A gets packet bits 48 76 LTLTLTLDIDCCSR DIDMSB gets 0s LTLDIDCCSR DID gets packet bits 16 23 LTLDIDCCSR SIDMSB gets 0s LTLDIDCCSR SID gets bits 24 31 LTLCCCSR FT gets packet bits 12 15 LTLCCCSR TT gets packet bits 32 35 LTLCCCSR MI gets 0s For a large transport packet it uses...

Page 690: ...ambs Swrite request hits overlapping ATMU windows Refer to Section 16 2 5 4 2 Window Boundary Crossing Errors on page 16 22 Packet is checked as a non SWRITE packet Yes if LTLEECSR IACB is set LTLEDCSR IACB No RapidIO packet is dropped Address WdPtr Xambs Not UT Request hits a protected ATMU window or the local configuration space window Packet is checked as non Swrite packet Yes if LTLEECSR ITD i...

Page 691: ... consumers The message unit is compliant with the message passing logical specification in the RapidIO Interconnect Specification Revision 1 2 The message passing model is most commonly used in systems in which a processing element is allowed to access only memory that is local to itself processing elements communicate with each other through message passing and communication is address independen...

Page 692: ...des Direct mode Software programs the necessary registers to point to the beginning of the message in memory Chaining mode Software programs the necessary registers to point to the beginning of the first valid descriptor in memory The descriptor provides all the necessary registers to start the message transfer Multicast mode A single segment message can be sent to multiple destinations Multicast ...

Page 693: ...word count OMxDCR If multicast mode is enabled OMxMR MM initialize the multicast group and list in OMxMGR and OMxMLR 4 Initialize the outbound message mode register message unit transfer mode bit OMxMR MUTM 1 to indicate direct mode Other control parameters must also be initialized in the mode register 5 Clear and then set the mode register message unit start bit OMxMR MUS to start the message tra...

Page 694: ...outbound message interrupt is generated if the end of message outbound message interrupt event is enabled OMnDATR EOMIE In Direct mode the outbound message interrupt is generated after a message operation completes if OMxDATR EOMIE 1 The event causing this interrupt is indicated by OMxSR EOMI The interrupt is held until the OMxSR EOMI bit is cleared by writing a 1 to it In Direct mode the Error Po...

Page 695: ...ops after the message operation completes indicated by OMxSR MUB Packet Response Time Out Sets the packet response time out status bit OMxSR PRT Generates a serial RapidIO error write port interrupt if OMxMR EIE is set Stops after the message operation completes indicated by OMxSR MUB Retry Error Threshold Exceeded Sets the retry threshold exceed status bit OMxSR RETE Generates a Serial RapidIO er...

Page 696: ...sted in step 1 16 3 2 3 Disabling and Enabling the Message Controller Once the message controller is started it cannot be stopped except by loss of power or reset 16 3 2 4 Hardware Error Handling Table 16 24 describes Direct mode hardware errors The error checking level indicates the order in which errors are checked Multiple errors can be checked at an error checking level When an error is detect...

Page 697: ...rror write port if LTLEECSR TSE is set Status bit set Illegal transaction target in the Logical Transport Layer Error Detect CSR LTLEDCSR ITTE Transport size error in the Logical Transport Layer Error Detect CSR LTLEDCSR TSE Message segment sent Yes Logical Transport Layer Capture Register Updated with the packet 2 Comments Packet is ignored and discarded Message response Large transport size when...

Page 698: ...in the Logical Transport Layer Error Detect CSR LTLEDCSR ITD Message segment sent Yes Logical Transport Layer Capture Register Updated with the packet 2 Comments Packet is ignored and discarded Message response Letter mbox and msgseg not outstanding or letter mbox not outstanding Error checking level 4b Interrupt generated Serial RapidIO error write port if LTLEECSR UR is set Status bit set Unsoli...

Page 699: ...equeue pointer is not incremented in chaining mode Notes 1 Notes 1 These error types are actually detected in the RapidIO port not in the message controller 2 In small transport size configuration using the packet the following allocations are made LTLACCSR XA gets the extended address packet bits 78 79 LTLACCSR A gets the address packet bits 48 76 LTLDIDCCSR MDID gets 0 LTLDIDCCSR DID gets the le...

Page 700: ... eight entries four of which are valid The local processor enqueues descriptors and the outbound message controller dequeues the descriptors Figure 16 9 Outbound Frame Queue Structure Table 16 25 Outbound Message Direct Mode Programming Errors Error Interrupt Generated Status Bit Set Comments Double word count greater than 256 bytes when multi cast mode selected No None Undefined operation Double ...

Page 701: ... multicast mode set OMxMR MM 7 Configure the other control parameters in the mode register OMxMR 8 Clear OMxSR MER PRT RETE TE QOI QFI EOMI and QEI If OMxSR MER PRT RETE TE or QOI are not cleared the message controller does not start a new message operation Incorrect status is indicated if the other status bits are not cleared 9 Set the message unit start OMxMR MUS to enable the outbound message c...

Page 702: ... message read to local memory completes the message is sent 10 If multi cast is enabled all the indicated targets are sent the same message 11 A non multicast message transfer completes after all message segments complete A multi cast message transfer completes after all message segments complete for each destination A message segment completes when one of the following occurs Done response receiv...

Page 703: ...Preventing Queue Overflow in Chaining Mode Software must guarantee that descriptors are not added to an already full queue When the increment bit is used OMxMR MUI software can poll the queue full bit OMxSR QF before enqueueing another descriptor When software sets the enqueue pointer directly software is responsible for not overflowing the descriptor queue 16 3 2 5 3 Switching Between Direct and ...

Page 704: ...operation After the message controller reads the descriptor from memory this field is loaded into the Source Address Register Destination port Destination port of the message operation After the message controller reads the descriptor from memory this field is loaded into the Destination Port Register Destination attributes Transaction attributes of the message operation After the message controll...

Page 705: ...upt can be generated for the following reasons in Chaining mode Message error response Message error response is received and this interrupt event is enabled OMxMR EIE Packet response time out A packet response time out occurs and this interrupt event is enabled OMxMR EIE Retry error threshold exceeded A retry threshold exceeded error occurs and this interrupt event is enabled OMxMR EIE Transactio...

Page 706: ...age controller has stopped by polling OMxSR MUB 3 Disables the message controller by clearing OMxMR MUS 4 Clears the error by writing a 1 to the corresponding OMxSR status bit listed in step 1 Transaction error Sets the transaction error bit OMxSR TE Does not generate message segment reads and sends no message segments if the internal error occurs while the memory controller reads descriptor memor...

Page 707: ...ription Message request Internal error during a read of the descriptor from local memory Error checking level 0 Interrupt generated Serial RapidIO error write port if OMxMR EIE is set Status bit set Transaction error in the outbound message status register OMxSR TE Message Failed in the Mailbox CSR MCSR FA Message segment sent No Logical Transport Layer Capture Register Comments Message controller...

Page 708: ...a message as soon as all message segments are transmitted 16 3 3 Inbound Message Controller Operation The inbound message controller receives messages and places them in a circular frame queue in local memory It can receive segments of a message in any order The address to which a message is to be written is computed as Base address msgseg ssize in double words In contrast to the outbound message ...

Page 709: ...size aligned that is they must be aligned on a boundary equal to the number of queue entries frame size in byte For example if there are eight entries in the queue and the frame size is 128 bytes the register must be 1024 byte aligned 2 Clear the status register IMxSR 3 In the inbound message mode register IMxMR set the mailbox enable bit IMxMR ME along with the other control parameters frame queu...

Page 710: ...ing occurs The memory write completes either successfully or with an internal error A message request time out occurs all message segments not yet received are now complete 5 The message segments of one message can immediately be followed by the message segments of another message under the following conditions If a message segment of a new message arrives before all memory writes complete for the...

Page 711: ...ting a 1 to the IMxSR MIQI bit 16 3 3 3 Message Steering Messages are forwarded to the inbound message controllers as follows Messages directed to mailbox 0 are forwarded to message controller 0 Messages directed to mailbox 1 2 or 3 are forwarded to message controller 1 16 3 3 4 Retry Response Conditions The conditions to generate a logical layer retry response retry are as follows The local memor...

Page 712: ...d for the following reasons An interrupt is generated after a message request time out and this interrupt event is enabled IMxMR EIE The message request time out counter starts after the first valid segment of a multi segment message is received and the time out counter is enabled A transaction error interrupt is generated after an internal error response is received and this interrupt event is en...

Page 713: ...RT and or IMxSR TE 2 Verifies that the message controller has stopped operation by polling IMxSR MB 3 Disables the message controller by clearing IMxMR ME 4 Clears the error by writing a 1 to the corresponding status bit IMxSR MRT and or IMxSR TE 16 3 3 7 Hardware Error Handling Table 16 31 lists the hardware error conditions The error checking level indicates the order in which errors are checked...

Page 714: ...ransport Layer Capture Register Updated with the packet Comments Packet is ignored and discarded An error or illegal transaction target error response is not generated Illegal destination ID1 Error checking level 1 Interrupt generated Serial RapidIO error write port if LTLEECSR ITTE is set Status bit set Illegal transaction target in the Logical Transport Layer Error Detect CSR LTLEDCSR ITTE Queue...

Page 715: ...Layer Capture Register Updated with the packet Comments Packet is ignored and discarded Not an error The RapidIO priority is not consistent for all message segments of a message Error checking level 2 Interrupt generated Status bit set Queue entry written in local memory Yes Response status Done or retry Logical Transport Layer Capture Register Comments Retry response occurs if the higher priority...

Page 716: ...ort Layer Error Detect CSR LTLEDCSR UT Queue entry written in local memory No Response status Error Logical Transport Layer Capture Register Updated with the packet Comments Packet is ignored and discarded This error applies only if a mailbox is not supported This error is not currently supported since all mailboxes are supported Message controller disabled and message received Error checking leve...

Page 717: ...ut update memory The enqueue pointer is not incremented The message operation completes Notes 1 These error types are actually detected in the RapidIO port not in the message controller 2 In small transport size configuration using the packet the following allocations are made LTLACCSR XA gets the extended address packet bits 78 79 LTLACCSR A gets the address packet bits 48 76 LTLDIDCCSR MDID gets...

Page 718: ...e received a message request time out must occurs and all pending frame queue writes must complete before message busy clears IMxSR MB Table 16 32 Inbound Message Programming Errors Error Interrupt Status Bit Set Comments Reserved value of the message in queue threshold IMxMR MIQ_THRESH or reserved value of the circular frame queue size IMxMR CIRQ_SIZE No No Undefined operation results The message...

Page 719: ...t of run time registers 16 4 1 Features Support for one outbound doorbell controllers Support for one inbound doorbell controllers The doorbell controller can sustain back to back inbound doorbells Table 16 33 MCSR Bits to Indicate Status of Inbound and Outbound Controllers MCSR Bit Description Available A Indicates the following The inbound message controller is enabled IMxMR ME The inbound messa...

Page 720: ...write completes as long as the RapidIO priority is the same or lower than the previous doorbell The doorbell is retried if the RapidIO priority is higher than the previous doorbell Table 16 12 depicts an example of the structure of the inbound doorbell queue and pointers The doorbell queue has eight entries three of which are currently valid The doorbell controller enqueues doorbells and the local...

Page 721: ... to ensure that the outbox is not busy see Table 16 120 ODSR Field Descriptions on page 16 188 2 Clear the following ODSR status bits MER RETE PRT EODI 3 Initialize the following registers Destination port ODDPR see page 16 189 Destination attributes ODDATR see page 16 190 Retry error threshold ODRETCR see page 16 191 4 To start the doorbell transfer clear and then set the doorbell start bit ODMR ...

Page 722: ... occurs and the Serial RapidIO error write port interrupt is generated software takes the following actions 1 Determines the cause of the interrupt and processes the error 2 Verifies that the doorbell controller has stopped operation by polling ODSR DUB 3 Disables the doorbell controller by clearing ODMR DUS 4 Clears the error by writing a 1 to the corresponding ODSR status bit see Table 16 120 OD...

Page 723: ...rocessed in a pipeline The first error detected in the processing pipeline updates the error management extensions registers These error condition checks are provided by the messaging unit These check are in addition to the error condition checks provided by the RapidIO port as discussed in Section 16 2 10 Errors and Error Handling on page 16 25 Table 16 35 Outbound Doorbell Hardware Errors Transa...

Page 724: ...ing level 1 Interrupt generated Serial RapidIO error write port if LTLEECSR ITD is set Status bit set Illegal transaction decode in the Logical Transport Layer Error Detect CSR LTLEDCSR ITD see page 16 131 Doorbell sent Yes Logical Transport Layer Capture Register Updated with the packet 2 Comments Packet is ignored and discarded Doorbell response RapidIO priority is less than or equal to outbound...

Page 725: ...es exceeds limit Error checking level 3 Interrupt generated Serial RapidIO error write port if LTLEECSR RETE is set see page 16 132 Serial RapidIO error write port if ODMR EIE is set see page 16 187 Status bit set Retry limit exceeded in the Logical Transport Layer Error Detect CSR LTLEDCSR RETE see page 16 131 ODSR RETE bit is set see page 16 188 Doorbell sent Yes Logical Transport Layer Capture ...

Page 726: ...MDID gets 0 LTLDIDCCSR DID gets the least significant byte of the destination ID packet bits 16 23 LTLDIDCCSR MSID gets 0 LTLDIDCCSR SID gets the least significant byte of the source ID packet bits 24 31 LTLCCCSR FT gets the ftype packet bits 12 15 LTLCCCSR TT gets the ttype packet bits 32 35 LTLCCCSR MI gets 0 In large transport size configuration using the packet the following allocations are ma...

Page 727: ...y write completes the enqueue pointer is incremented to point to the next doorbell queue entry in local memory 4 If another doorbell arrives before all previous doorbell memory writes complete and the RapidIO priority of the doorbell is equal to or lower than the priority of all previous doorbells the doorbell controller processes the doorbell and generates a memory write to the appropriate doorbe...

Page 728: ...ntical for all received doorbell entries Figure 16 13 depicts the doorbell queue entry fields and their related offsets Figure 16 13 Doorbell Entry Format Table 16 37 Inbound Doorbell Target Info Definition Bit Name Description 31 16 Reserved 15 8 ETID Extended target ID in Large Transport mode Reserved for Small Transport mode 7 0 TID Target ID field from the received doorbell packet Table 16 38 ...

Page 729: ...DSR DIQI bit is cleared by writing a 1 to it The circular queue contains one or more doorbells the specified number of doorbells has not accumulated a doorbell has not been dequeued for the maximum interrupt report interval and this interrupt event is enabled IDMR DIQIE The event causing this interrupt is indicated by IDSR DIQI The interrupt is held until either IDMR DI is set or DQDPAR DQDPA is w...

Page 730: ...ror detected in the processing pipeline updates the error management extensions registers These error condition checks are provided by the messaging unit These checks are in addition to the error condition checks provided by the RapidIO port as discussed in Section 16 2 10 Errors and Error Handling on page 16 25 Table 16 39 Inbound Doorbell Hardware Errors Error Description Reserved ftype1 Error c...

Page 731: ... Logical Transport Layer Error Detect CSR LTLEDCSR UT Queue Entry Written in local memory No Response status Error Logical Transport Layer Capture Register Updated with packet 2 Comments Packet is ignored and discarded Inbound doorbell packet with a RapidIO priority of 3 Error checking level 2 Interrupt generated Serial RapidIO error write port if LTLEECSR ITD is set Status bit set Illegal transac...

Page 732: ...pture Register Comments An internal error may or may not occur during the subsequent write of a doorbell queue entry to memory Notes 1 These error types are actually detected in the RapidIO port not in the doorbell controller 2 In small transport size configuration using the packet the following allocations are made LTLACCSR XA gets the extended address packet bits 78 79 LTLACCSR A gets the addres...

Page 733: ...address register DQEPAR must be initialized to the same value for proper doorbell controller operation Table 16 40 Inbound Doorbell Programming Errors Error Interrupt Generated Status Bit Set Comments Reserved value of the doorbell in queue threshold IDxMR DIQ_THRESH or reserved value of the circular doorbell queue size IDxMR CIRQ_SIZ see Table 16 124 IDMR Field Descriptions on page 16 192 No No U...

Page 734: ... state of the inbound doorbell controller busy bit IDSR DUB Failed PWDCSR FA This bit reflects the state of the transaction error status bit IDSR TE Error PWDCSR ERR This bit is always a 0 16 5 Port Write Controller The implementation of the port write controller is very similar to the inbound message and doorbell controllers except that only one queue entry is supported The port write is an error...

Page 735: ...he value of the port write queue base address registers IPWQBAR Valid payload sizes include 4 8 16 24 32 40 48 56 or 64 bytes Note that 64 bytes are always written to memory If the actual payload size is less than 64 bytes the non payload data is undefined 3 If the queue full interrupt enable bit is set IPWMR QFIE after the memory write completes the port write controller generates the error port ...

Page 736: ...e the queue full bit is set or a port write is being written to memory but has not completed all received port writes are discarded When a port write is discarded for one of these reasons the controller sets the port write discarded bit IPWSR PWD Note that the port write busy bit IPWSR PWB indicates that a port write is being written to memory but has not completed 16 5 5 Transaction Errors When a...

Page 737: ... Handling on page 16 25 Table 16 41 Inbound Port Write Hardware Errors Error Description Reserved ftype1 Error checking level 1 Interrupt generated Serial RapidIO error write port if LTLEECSR UT is set Status bit set Unsupported transaction in the Logical Transport Layer Error Detect CSR LTLEDCSR UT Queue Entry Written in local memory No Response status No response Logical Transport Layer Capture ...

Page 738: ...t Layer Error Detect CSR LTLEDCSR ITD Queue Entry Written in local memory No Response status No response Logical Transport Layer Capture Register Updated with packet 2 Comments Packet is ignored and discarded Inbound maintenance port write received and inbound maintenance port writes are not supported as indicated by DOCAR PW 1 Error checking level 1 Interrupt generated Serial RapidIO error write ...

Page 739: ... LTLDIDCCSR DID gets the least significant byte of the destination ID packet bits 16 23 LTLDIDCCSR MSID gets 0 LTLDIDCCSR SID gets the least significant byte of the source ID packet bits 24 31 LTLCCCSR FT gets the ftype packet bits 12 15 LTLCCCSR TT gets the ttype packet bits 32 35 LTLCCCSR MI gets 0 In large transport size configuration using the packet the following allocations are made LTLACCSR...

Page 740: ... port write controller status bits These read only status bits only indicate the state of the port write controller See Section 16 6 9 Port Write and Doorbell Command and Status Register PWDCSR on page 16 112 for details Available PWDCSR PA Indicates that the port write controller is enabled IPWnMR PWE the only port write queue entry is available to be written IPWnSR QF 0 and the port write contro...

Page 741: ...e 16 115 Base Device ID Command and Status Register BDIDCSR page 16 116 Host Base Device ID Lock Command and Status Register HBDIDLCSR page 16 117 Component Tag Command and Status Register CTCSR page 16 118 Extended Features Space 1x 4x LP Serial Port Maintenance Block Header 0 PMBH0 page 16 119 Port Link Time Out Control Command and Status Register PLTOCCSR page 16 120 Port Response Time out Cont...

Page 742: ...te Threshold Command and Status Register P0ERTCSR page 16 145 Implementation Space General Logical Layer Configuration Register LLCR page 16 146 Error Port write Interrupt Status Register EPWISR page 16 147 Logical Retry Error Threshold Configuration Register LRETCR page 16 148 Physical Retry Error Threshold Configuration Register PRETCR page 16 149 Port 0 Alternate Device ID Command and Status Re...

Page 743: ...utbound Message x Destination Port Registers OMxDPR page 16 173 Outbound Message x Destination Attributes Registers OMxDATR page 16 174 Outbound Message x Double Word Count Registers OMxDCR page 16 175 Outbound Message x Retry Error Threshold Configuration Registers OMxRETCR page 16 177 Outbound Message x Multicast Group Registers OMxMGR page 16 178 Outbound Message x Multicast List Registers OMxM...

Page 744: ...00 Note The base address for the RapidIO registers is 0xFFF80000 16 6 1 Device Identity Capability Register DIDCAR DIDCAR Device Identity Capability Register Offset 0x00000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DI TYPE R RESET 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DVI TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table 16 43 DIDCAR Field Description...

Page 745: ... is assigned and managed by the vendor specified by DIDCAR DVI AIDCAR Assembly Identity Capability Register Offset 0x00008 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AI TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AVI TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 45 AIDCAR Field Descriptions Bit Name Description AI 31 16 0x0000 Assembly Id...

Page 746: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 AR TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFP TYPE R RESET 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Table 16 46 AICAR Field Descriptions Bit Reset Description AR 31 16 0x0000 Assembly Revision EFP 15 0 0x0100 Extended Features Pointer PEFCAR Processing Element Features Capability Register Offset 0x00010 Bit 31 30 29 28 ...

Page 747: ...b1111 Mailbox Specifies the inbound mailboxes supported by the MSC8144E 1000 Mailbox 0 supported by MSC8144E 0100 Mailbox 1 supported by MSC8144E 0010 Mailbox 2 supported by MSC8144E 0001 Mailbox 3 supported by MSC8144E 1111 Mailboxes 0 3 DB 19 1 Doorbell Specifies whether the RapidIO Controller supports inbound Doorbells 18 5 0 Reserved Write to zero for future compatibility CTLS 4 1 Common Trans...

Page 748: ...upport IR 30 0 IRead Operation MSC8144E does not support RO 29 0 Read to Own Operation MSC8144E does not support DCI 28 0 Data Cache Invalidate Operation MSC8144E does not support C 27 0 Castout Operation MSC8144E does not support F 26 0 Flush Operation MSC8144E does not support IOR 25 0 I O Read Operation MSC8144E does not support ICI 24 0 Instruction Cache Invalidate Operation MSC8144E does not ...

Page 749: ...tion MSC8144E does not support 1 0 0 Reserved Write to zero for future compatibility DOCAR Destination Operations Capability Register 0x0001C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R IR RO DCI C F IOR ICI TIE TIES TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NR NW SW NWR M D ATS AI AD AS AC PW TYPE R RESET 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 Table...

Page 750: ...ation Supported NWR 12 1 Nwrite_R Operation Supported M 11 1 Message Operation Supported D 10 1 Doorbell Operation Supported 9 Reserved Write to zero for future compatibility ATS 8 0 Atomic Test and Swap Operation MSC8144E does not support AI 7 0 Atomic Inc Operation MSC8144E does not support AD 6 0 Atomic Dec Operation MSC8144E does not support AS 5 0 Atomic Set Operation MSC8144E does not suppor...

Page 751: ...ll EM0 29 1 Empty Specifies whether message controller 0 contains outstanding messages 0 Contains outstanding messages 1 Contains no outstanding messages B0 28 0 Busy Specifies whether message controller 0 is busy processing a message When this bit is set new message operations to message controller 0 return retry responses 0 Not busy 1 Busy FA0 27 0 Failure Specifies whether message controller 0 ...

Page 752: ...0 No internal error 1 Internal fault or error condition encountered ERR1 18 0 Error This field always returns a value of 0 17 0 0 Reserved Write to zero for future compatibility PWDCSR Port Write and Doorbell Command and Status Register Offset 0x00044 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A FU EM B FA ERR TYPE R RESET 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 753: ...en this bit is cleared all incoming port write packets are discarded 0 Not available 1 Ready PFU 6 0 Port Write Unit Full Specifies whether the port write unit is full When this bit is set all incoming port write packets are discarded 0 Not full 1 Full PEM 5 1 Port Write Unit Empty This field always returns a value of 1 PB 4 0 Port write Unit Busy Specifies whether the port write unit is busy proc...

Page 754: ...Processing Element Logical Layer Offset 0x0004C Control Command and Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EAC TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 16 52 PELLCCSR Field Descriptions Bit Reset Description 31 3 0 Reserved Write to zero for future compatibility EAC 2 0 0b0...

Page 755: ...gisters an external processor writing to LCSBA1CSR should not assume that the write occurs until a response is received LCSBA1CSR Local Configuration Space Base Address 1 Offset 0x0005C Command and Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LCSBA TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 756: ... TYPE R W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 16 54 BDIDCSR Field Descriptions Bit Reset Description 31 24 0 Reserved Write to zero for future compatibility BDID 23 16 0xFF Base Device ID in Small Common Transport System RapidIO Device ID Valid only if PEFCAR CTLS is cleared If the RapidIO controller is configured as a host BDID 0x00 If the RapidIO controller is configured as an agent BDID...

Page 757: ...ce ID lock CSR to verify that it owns the lock before it attempts to initialize the device HBDIDLCSR Host Base Device ID Lock Command and Status Offset 0x00068 Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HBDID TYPE R RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 16 55 HBDIDLCSR Field Descriptions ...

Page 758: ...can assign when the device is initialized It is unused internally in RapidIO Endpoint CTCSR Component Tag Command and Status Register Offset 0x0006C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CT TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CT TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 56 CTCSR Field Descriptions Bit Reset Descriptio...

Page 759: ...tware assisted error recovery are supported software assisted error recovery is not Therefore the RapidIO Endpoint is defined here as not supporting software assisted error recovery PMBH0 Port Maintenance Block Offset 0x00100 Header 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EFPTR TYPE R RESET 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFID TYPE R RESET 0 ...

Page 760: ...mum time out interval and represents between 3 and 5 seconds PLTOCCSR Port Link Time Out Control Command and Status Offset 0x00120 Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TV TYPE R W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TV TYPE R W R RESET 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Table 16 58 PLTOCCSR Field Descriptions Bit Reset Description TV...

Page 761: ...lies to RapidIO Endpoint and the messaging unit PRTOCCSR Port Response Time Out Control Command and Status Offset 0x00124 Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TV TYPE R W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TV TYPE R W R RESET 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Table 16 59 PRTOCCSR Field Descriptions Bit Reset Description TV 31 8 0xF...

Page 762: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 60 PGCCSR Field Descriptions Bit Reset Description Settings H 31 0 Host Determines the host agent configuration for the device Notice that by default H 0 0 Agent device 1 Host device M 30 1 Initiator The value of this bit is identical to that of GCCSR H which is assigned by power on reset configuration signals Setting M 0 disables all outbound transactions and pr...

Page 763: ...upported Table 16 61 lists P0LMREQCSR fields P0LMREQCSR Port 0 Link Maintenance Request Offset 0x00140 Command and Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 61 P0LMREQCSR Field Descriptions Bit Reset Description 31 3 0 Reserved...

Page 764: ...0 9 8 7 6 5 4 3 2 1 0 AS LS TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 62 P0LMRESPCSR Field Descriptions Bit Reset Description Settings RV 31 0 Response Valid This bit indicates one of two conditions If the link request causes a link response a set bit indicates that the link response was received and the status fields are valid If the link request did not cause a link response a set bi...

Page 765: ...12 11 10 9 8 7 6 5 4 3 2 1 0 OUTA OBA TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 63 P0LASCSR Field Descriptions Bit Reset Description 31 29 0 Reserved Write as zero for future compatibility IA 28 24 0 Input ackID The value of the next expected Input port ackID 23 13 0 Reserved Write as zero for future compatibility OUTA 12 8 0 Outstanding Port Unacknowledged ackID Status Next expect...

Page 766: ...ins set until it is written with a logic 1 to clear it OFE 25 0 Output Fail Encountered The output port has encountered a failed condition because the error rate counter PnEERCSR ERC has met or exceeded the port failed error threshold PnERTCSR ERFTT OFE remains set until it is written with a logic 1 to clear it When it is cleared it does not assert again unless the error rate counter dips below th...

Page 767: ... 7 5 0 Reserved Write to zero for future compatibility PWP 4 0 Port Write Port has encountered a condition requiring it to initiate a maintenance port write operation PWP is valid only if the device can issue a maintenance port write transaction RapidIO Endpoint cannot issue port writes This bit is hard wired to 0 Read only 3 0 Reserved PE 2 0 Port Error The input or output port has encountered an...

Page 768: ...rades to 1x the value changes to 0b000 000 Single lane port lane 0 001 Reserved 010 Four lane port the default 011 111 Reserved PWO 26 24 0b000 Port Width Override Soft port configuration to override the hardware size Change PWO only when the port is uninitialized First disable the RapidIO port Then change PWO to any valid value Finally re enable the RapidIO port 000 No override the default 001 Re...

Page 769: ... 19 0 Multicast Event Participant This bit is hard wired to 0 The MSC8144E does not participate in multicast events 18 4 0 Reserved Write to zero for future compatibility SPF 3 0 Stop on Port Failed Encounter Enable Used with the DPE bit to force certain behavior when the error rate failed threshold is met or exceeded 0 Stop on port failed disabled 1 Stop on port failed enabled DPE 2 0 Drop Packet...

Page 770: ...bits to be set The priority of errors is PRT and all other errors An error that is not enabled sets the detect bit in this register as long as a capture has not yet occurred You can program fields in this ERBH Error Reporting Block Header Offset 0x00600 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EFPTR TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E...

Page 771: ... the specified time out interval The error is detected and captured in message unit PRT 24 0 Packet Response Time Out Indicates that a required response was not received within the specified time out interval IO MSG logical UR 23 0 Unsolicited Response Indicates that an unsolicited unexpected response packet was received IO MSG logical UT 22 0 Unsupported Transaction Indicates a received transacti...

Page 772: ...ge Format Error Enable Enables reporting of a message format error It captures and locks the error Capture done in messaging unit ITD 27 0 Illegal Transaction Decode Error Enable Enables reporting of an illegal transaction decode error It captures and locks the error ITTE 26 0 Illegal Transaction Target Error Enable Enables reporting of an illegal transaction target error It captures and locks the...

Page 773: ...les reporting when the allowed number of logical retries is exceeded TSE 3 0 Transport Size Error Enable Enables error reporting when the field is not consistent with the CTLS bit of the processing element features CAR that is the tt value is reserved or indicates a common transport system unsupported by this device PTTL 2 0 Packet Time to Live Error Enable Enables reporting of a packet time to li...

Page 774: ...ed address bits of the address associated with the error for requests responses if available For details see Section 16 2 10 3 Logical Layer RapidIO Errors on page 16 30 LTLDIDCCSR Logical Transport Layer Device ID Capture Command Offset 0x00618 and Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DIDMSB DID TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 ...

Page 775: ...0 Source ID Normally the source ID or least significant byte of the source ID if large transport system associated with the error For details see Section 16 2 10 3 Logical Layer RapidIO Errors on page 16 30 LTLCCCSR Logical Transport Layer Control Capture Command and Offset 0x0061C Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FT TT MI TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 776: ...ed a control symbol with a bad CRC value AUA 21 0 Acknowledge Control With Unexpected Acknowledge ID Received an acknowledge control symbol with an unexpected acknowledge ID packet accepted or packet retry PNA 20 0 Packet Not Accepted Received packet not accepted acknowledge control symbol UA 19 0 Unexpected Acknowledge ID Received packet with unexpected ackID value CRC 18 0 Bad CRC Received a pac...

Page 777: ...r rate counting of an acknowledge control symbol with an unexpected acknowledge ID PNA 20 0 Packet Not Accepted Enable Enable error rate counting of packet not accepted acknowledge control symbols UA 19 0 Unexpected Acknowledge ID Enable Enable error rate counting of packets with an unexpected ackID value CRC 18 0 Bad CRC Enable Enable error rate counting of packets with a bad CRC value EM 17 0 Ex...

Page 778: ...4 23 22 21 20 19 18 17 16 IT ET ECI15 ECI14 ECI13 ECI12 ECI11 ECI10 ECI9 ECI8 TYPE R W R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECI7 ECI6 ECI5 ECI4 ECI3 ECI2 ECI1 ECI0 CVI TYPE R W R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 74 P0ECACSR Field Descriptions Bit Reset Description Settings IT 31 30 0 Information Type Type of information logged 00 P...

Page 779: ...R00 15 8 ECI12 Associated with PnPCSECCSR0 7 0 ECI11 Associated with PnPECCSR1 31 24 ECI10 Associated with PnPECCSR1 25 16 ECI1 Associated with PnPECCSR3 15 8 ECI0 Associated with PnPECCSR3 7 0 7 1 0 Reserved Write to zero for future compatibility CVI 0 0 Contain Valid Information Hardware sets CVI to indicate that the packet control symbol capture registers contain valid information For control s...

Page 780: ... by the port Software should verify that the P0ECACSR CVI bit is set before reading the capture registers to ensure that the error is properly captured P0PCSECCSR0 Port 0 Packet Control Symbol Error Capture Command Offset 0x0064C and Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C0 TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 TYP...

Page 781: ...are should verify that the P0ECACSR CVI bit is set before reading the capture registers to ensure that the error is properly captured P0PECCSR1 Port 0 Packet Error Capture Command and Offset 0x00650 Status Register 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C1 TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0...

Page 782: ...oftware should verify that the P0ECACSR CVI bit is set before reading the capture registers to ensure that the error is properly captured P0PECCSR2 Port 0 Packet Error Capture Command and Status Register 2 Offset 0x00654 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C2 TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 TYPE R W RESET 0 0 0 0 0 0 0 0 0...

Page 783: ...tware should verify that the P0ECACSR CVI bit is set before reading the capture registers to ensure that the error has been properly captured P0PECCSR3 Port 0 Packet Error Capture Command and Offset 0x00658 Status Register 3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C3 TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 TYPE R W RESET 0 0 0 0 0 0 0...

Page 784: ...ecrement every 1 s 34 0x10 Decrement every 10 s 34 0x20 Decrement every 100 s 34 0x40 Decrement every 1000 s 34 0x80 Decrement every 10000 s 34 Other values are reserved and cause undefined operation 23 18 0 Reserved Write to zero for future compatibility ERR 17 16 0 Error Rate Limits increments of the error rate counter above the failed threshold trigger This counter never increments above 0xFF e...

Page 785: ...Threshold Trigger Provides the threshold value for reporting an error condition due to a possibly broken link The PnESCSR OFE bit is set if PnERCSR ERC exceeds the ERFTT value 0x00 Disable the error rate failed threshold trigger 0x01 Set the error reporting threshold to 1 0x02 Set the error reporting threshold to 2 0xFF Set the error reporting threshold to 255 ERDTT 23 16 0xFF Error Rate Degraded ...

Page 786: ... 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 81 LLCR Field Descriptions Bit Reset Description 31 30 0 Reserved Write to zero for future compatibility ECRAB 29 0 External Configuration Register Access Block Blocks all maintenance requests and accesses to LCSBA1CSR Reads return all 0s and writes are ignored both return a don...

Page 787: ...alent copy EPWISR Error Port Write Interrupt Status Register Offset0x10010 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PINT TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MU PW TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 82 EPWISR Field Descriptions Bit Reset Description PINT 31 0 Physical or Logical Transport Error Interrupt Indicates a ph...

Page 788: ...d LRETCR Logical Retry Error Threshold Configuration Register Offset0x10020 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET TYPE R RESET 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 16 83 LRETCR Field Descriptions Bit Reset Description 31 8 0 Reserved Write to zero for future compatibility RET 7 0 0xFF Retry Er...

Page 789: ...0080 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET TYPE R R W RESET 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 16 84 PRETCR Field Descriptions Bit Reset Description Settings 31 8 0 Reserved Write to zero for future compatibility RET 7 0 0xFF Retry Error Threshold The threshold value for the number of consec...

Page 790: ...O endpoint generates requests using only the device ID in P0ADIDCSR It generates responses with the deviceID in the original request packet either from P0ADIDCSR or BDIDCSR The selection between a large or small transport system is done during the power up sequence by using the CTLS bit in the RCW P0ADIDCSR Port 0 Alternate Device ID Command and Status Register Offset0x10100 Bit 31 30 29 28 27 26 ...

Page 791: ...it 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AA TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 86 P0AACR Field Descriptions Bit Name Description Settings 31 1 0 Reserved Write to zero for future compatibility AA 0 0 Accept All Specifies whether packet acceptance is based on a target ID When this bit is set the tt field value must be consistent with the common transport system specified by t...

Page 792: ...g stalled when packets cannot be successfully transmitted acknowledged with an accept by the link partner at the physical level The value of this register should always be larger than the link time out value PLTOCCSR The reset value is the maximum time out interval and represents between 3 and 5 seconds When the packet time to live counter expires P0PCR OBDEN is automatically set P0PCR OBDEN must ...

Page 793: ...ET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 88 P0IECSR Field Descriptions Bit Reset Description RETE 31 0 Retry Error Threshold Exceeded Set when the number of consecutive retries reaches the retry error threshold in the Physical Retry Error Threshold Configuration Register PRETCR RETE is cleared by writing a va...

Page 794: ...uture compatibility CCC 15 1 CRC Checking Enable for Control Symbol CRC is checked on received control symbols When CCC is cleared no CRC is checked on received control symbols 14 13 0 Reserved Write to zero for future compatibility 12 5 0 Reserved Write to zero for future compatibility CCP 4 1 CRC Checking Enable for Packets CRC is checked on received packets When CCP is cleared no CRC is checked...

Page 795: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 91 P0SLCSR Field Descriptions Bit Reset Description LS0 31 0 Lane Sync Achieved for Lane 0 Write with 1 to clear LS1 30 0 Lane Sync Achieved for Lane 1 Write with 1 to clear LS2 29 0 Lane Sync Achieved for Lane 2 Write with 1 to clear LS3 28 0 Lane Sync Achieved for Lane ...

Page 796: ...Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EIC EIR TYPE R W R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EIR TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 92 P0SLEICR Field Descriptions Bit Reset Description Settings EIC 31 27 0 Error Injection Control Enables and controls serial link error injection as follows 00000 Error injection is di...

Page 797: ...0 1 0 0 0 0 0 0 0 0 Table 16 93 IPBRR1 Field Descriptions Bit Reset Description IPID 31 16 0x01C0 IP block ID 0x01C0 IPMJ 15 8 0x01 Major revision of the IP block 0x01 IPMN 7 0 0x00 Minor revision of the IP block 0x0 IPBRR2 IP Block Revision Register 2 Offset 0x10BFC Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IPINT TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6...

Page 798: ...tem This field is valid only if the PEFCAR CTLS bit is set see Section 16 6 5 Processing Element Features Capability Register PEFCAR on page 16 106 Bits 0 5 of the target ID are specified in the P0ROWTEARX see Section 16 6 53 Port 0 RapidIO Outbound Window Translation Extended Address Registers x P0ROWTEARx on page 16 159 TREXAD 29 20 0 Translation Extended Address TREXAD 0 7 corresponds to the ta...

Page 799: ...eserved for default window 0 P0ROWTEAR 0 8 Port 0 RapidIO Outbound Offset 0x10C04 x 0x20 Window Translation Extended Address Registers 0 8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTGTID TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 96 P0RIWTARx Field Descriptions Bit Reset Description 31 6 0 ...

Page 800: ... and read only 0 Window disabled 1 Window enabled 30 28 0 Reserved Write to zero for future compatibility TFLOWLY 27 26 Transaction Flow Level Selects the transaction flow priority level This field must be set to 00 if the PCI bit is set Also the RapidIO priority given by this field must always be greater than or equal to the internal priority or a deadlock can occur Normally the internal priority...

Page 801: ...requiring response sent from an internal source must generate a write requiring response to the RapidIO interface Therefore if an internal write requiring response request hits a window with WRTYP SWRITE or NWRITE the RapidIO endpoint generates an NWRITE_R instead 0011 SWRITE 0100 NWRITE 0101 NWRITE_R 0111 Maintenance Write All other values are reserved 11 6 Reserved Write to zero for future compa...

Page 802: ...1 8 Port 0 RapidIO Outbound Offset 0x10C08 x 0x20 Window Base Address Registers 1 8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BEXAD BADD TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BADD TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 98 P0ROWBARx Field Descriptions Bit Reset Description 31 24 0 Reserved Write to zero for future compa...

Page 803: ... Note This field must be set to 00 if the PCI bit is set 00 Lowest priority transaction request flow 01 Next highest priority transaction request flow 10 Highest priority transaction request flow 11 Reserved 25 24 Reserved Write to zero for future compatibility RDTYP 23 20 Read Type Transaction type to run on the RapidIO interface if the access is a read 0100 NREAD 0111 Maintenance read All other ...

Page 804: ...t 0 RapidIO Inbound Offset 0x10D60 4 x 0x20 Window Translation Address Registers 0 4 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TRAD TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRAD TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 100 P0RIWTARx Field Descriptions Bit Reset Description 31 20 0 Reserved Write to zero for future compatibility T...

Page 805: ...WBAR 1 4 Port 0 RapidIO Inbound Offset 0x10D68 4 x 0x20 Window Base Address Registers 1 4 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BEXAD BADD TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BADD TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 101 P0RIWBARx Field Descriptions Bit Reset Description 31 22 0 Reserved Write to zero for futur...

Page 806: ...PE R W R R W RESET 0000_0000_0000_0100 P0RIWAR 1 4 1000_0000_0000_0100 P0RIWAR 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRTYP SIZE TYPE R W R R W R for default window 0 RESET 0100_0000_0010_0001 P0RIWAR 0 4 Table 16 102 P0RIWARx Field Descriptions Bit Description Settings EN 31 Enable Address Translation Set to 1 and read only for default window 0 PW 30 Protected Window Indicates that this wind...

Page 807: ...N which is the encoded 2 N 1 byte window size The smallest window size is 4 KB This field is read only for default window 0 000000 Reserved 001011 4 KB window size 001100 8 KB window size 011111 4 GB window size 100000 8 GB window size 100001 16 GB window size 100010 Reserved 111111 Reserved OM 0 1 MR Outbound Message 0 1 Mode Registers Offset 0x13000 x 0x100 Bit 31 30 29 28 27 26 25 24 23 22 21 2...

Page 808: ...iptors 24 16 0 Reserved Write to zero for future compatibility CIRQ_SIZ 15 12 0 Circular Descriptor Queue Size Determines the number of descriptors that can be placed on the circular queue without overflow For proper operation this field should be modified only when the outbound message controller is not enabled 0000 2 0001 4 0010 8 0011 16 0100 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010...

Page 809: ... a port write error interrupt 4 3 0 Reserved Write to zero for future compatibility MUTM 2 0 Message unit Transfer Mode Puts the message unit into direct mode so that software is responsible for placing all the required parameters into registers to start the message transmission Clearing this bit configures the message unit in chaining mode 0 Chaining mode 1 Direct mode MUI 1 0 Message Unit Increm...

Page 810: ...ccurs during the message operation This bit is cleared by writing a value of 1 to it For proper operation this field should be modified only when the outbound message controller is not enabled 6 0 Reserved Write to zero for future compatibility QOI 5 0 Queue Overflow Interrupt Set when a queue overflow condition is detected This bit is cleared by writing a value of 1 to it QOI is applicable only t...

Page 811: ...e pointer indicates that a new descriptor was added to the queue and is ready for processing If the queue becomes empty and OMxMR QEIE is set OMxSR QEI is set and an interrupt is generated When software initializes these registers they must be aligned on a boundary equal to the number of queue entries 32 bytes the size of each queue descriptor For example if there are eight entries in the queue th...

Page 812: ...utbound Message 0 1 Source Offset 0x13014 x 0x100 Address Registers Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SAD TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAD TYPE R W R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 106 OMxSAR Field Descriptions Bits Reset Description SAD 31 3 0 Source Address The source address of the message operation Th...

Page 813: ...ended Destination Target Route Most significant byte of a 16 bit target route when activated in Large Transport mode Reserved when operated in Small Transport mode For proper operation this field should be modified only when the outbound message controller is not enabled DTGTROUTE 23 16 0 Destination Target Route Contains the target route field of the transaction device ID of the target This value...

Page 814: ...list Messages are limited to one segment and 256 bytes or less 0 Normal operation 1 Multicast mode 30 0 Reserved Write to zero for future compatibility EOMIE 29 0 End of Message Interrupt Enable When set generates an interrupt when the current message operation finishes For proper operation this field should be modified only when the outbound message controller is not enabled 28 0 Reserved Write t...

Page 815: ...ption Settings 31 13 0 Reserved Write to zero for future compatibility DCR 12 3 0 Transfer Count Register Contains the number of bytes for the message operation For proper operation this field should be modified only when the outbound message controller is not enabled The values with an asterisk apply only in Multi Segment mode Note The value in this register represents the number of double words ...

Page 816: ...and generates an interrupt OMxMR MUS must change from a 1 to a 0 to clear this error condition If the enqueue pointer is written directly the queue overflow condition is not detected If the enqueue and dequeue pointers were the same before the register is incremented the message unit controller will start if enabled Note When software initializes these registers they must be aligned on a boundary ...

Page 817: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 111 OMxRETCR Field Descriptions Bits Reset Description Settings 31 8 0 Reserved Write to zero for future compatibility RET 7 0 0 Retry Error Threshold The number of times the message unit can attempt to ...

Page 818: ...roup 0 MG 0 contains target device IDs 0 1 31 multicast group 1 MG 1 contains target device IDs 32 33 63 and so on In large transport mode the extended multicast group represents the eight most significant bits bits 15 8 the multicast group represents the next three bits bits 7 5 and the multicast list indicates a list of targets within that group If multicast is enabled this information in the mu...

Page 819: ...get Device ID For proper operation this field should be modified only when the outbound message controller is not enabled OM 0 1 MLR Outbound Message 0 1 Multicast List Offset 0x13034 x 0x100 Registers Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ML TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ML TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table ...

Page 820: ... the frame queue before Message In Queue is signaled Results are undefined if the message in queue threshold is greater than or equal to the message queue size IMxMR CIRQ_SIZ For proper operation this field should be modified only when the inbound message controller is not enabled 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 1111 Reserved 27 20 0 Re...

Page 821: ...mulated the number of messages specified by the IMxMR MIQ_THRESH No MIQ interrupt is generated if this bit is cleared If this bit is set and IMxSR MIQ 1 IMxSR MIQI is set If this bit is set and IMxMR MI is also set simultaneously IMxSR MIQI reflects the value of MIQ after the increment 0 No interrupt is generated 1 Interrupt generaated on message in queue event EIE 5 0 Error Interrupt Enable When ...

Page 822: ...Read only 19 17 0 Reserved Write to zero for future compatibility MIQ 16 0 Message In Queue If the queue has accumulated the number of messages specified by the IMxMR MIQTH this bit is set MIQ is cleared when the number of message in the queue is less than the number specified by IMxMR MIQ_THRESH and if the message controller is disabled Read only 15 11 0 Reserved Write to zero for future compatib...

Page 823: ...sage operation is in progress MB is cleared when an error occurs or the message operation finishes Read only QE 1 1 Queue Empty If the queue is empty this bit is set QE is also set if the message controller is disabled Read only MIQI 0 0 Message In Queue Interrupt If the queue has accumulated the number of messages specified by the IMxMR MIQ_THRESH and the IMxMR MIQIE bit is set this bit is set an...

Page 824: ...fter the processor increments them the queue is empty and all outstanding messages are processed When software initializes thesee registers they must be aligned on a boundary equal to the number of queue entries x frame size For example if there are eight entries in the queue and the frame size is 128 bytes the register must be 1024 byte aligned The number of queue entries is set in IMxMR CIRQ_SIZ...

Page 825: ...e the same before the register is incrememted the queue has changed from empty to not empty If IMxMR MIQIE is set IMxSR MIQI is set and an interrupt is generated When software initializes these registers they must be aligned on a boundary equal to the number of queue entries x frame size For example if there are eight entries in the queue and the frame size is 128 bytes the register must be 1024 b...

Page 826: ...d 5 seconds IM 0 1 MIRIR Inbound Message 0 1 Maximum Offsert 0x13078 x 0x100 Interrupt Report Interval Registers Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MIRI TYPE R W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIRI TYPE R W R RESET 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Table 16 118 IMxMIRIR Field Descriptions Bits Reset Description MIRI 31 8 0xFFFFFF Maxi...

Page 827: ...Offset 0x13400 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUS TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 119 ODMR Field Descriptions Bits Reset Description 31 1 0 Reserved Write to zero for future compatibility DUS 0 0 Doorbell Unit Start A 0 to 1 transition when the doorbell unit is not busy...

Page 828: ...ell operation is not in progress RETE 11 0 Retry Error Threshold Exceeded Set when the doorbell unit cannot complete a doorbell operation because the retry error threshold value has been exceeded due to a RapidIO retry response RETE is cleared by writing a 1 to it For proper operation this bit should be cleared only when a doorbell operation is not in progress PRT 10 0 Packet Response Time Out Set...

Page 829: ...t 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 121 ODDPR Field Descriptions Bits Reset Description EDTROUTE 31 24 0 Extended Destination Target Route Most significant byte of a 16 bit target route device ID of the target in Large Transport mode In Small Transport mode this bit is reserved For proper operation this field should be modified only when a ...

Page 830: ...doorbell operation finishes This field should be modified only when a doorbell operation is not in progress 28 0 Reserved Write to zero for future compatibility DTFLOWLVL 27 26 0 Transaction Flow Level Specifies the transaction flow level This field should be modified only when a doorbell operation is not in progress 00 Lowest priority transaction flow 01 Next highest priority transaction flow 10 ...

Page 831: ...RETCR Outbound Doorbell Retry Error Threshold Configuration Offset 0x1342C Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET TYPE R R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 123 ODRETCR Field Descriptions Bits Name Description Settings 31 8 0 Reserved Write to zero for future compatibilit...

Page 832: ...ell queue before the doorbell in queue bit is set IDSR DIQ Undefined operation results if the actual number of entries in the doorbell in queue threshold is set as greater than or equal to the actual size of the doorbell queue For proper operation this field should be modified only when the doorbell controller is not enabled 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 100...

Page 833: ...IQI is set If this bit is set and IDMR DI is set simultaneously IDSR DIQI reflects the value of DIQ after the increment For proper operation this field should only be modified when the inbound doorbell controller is not enabled 0 No DIQ interrupt is generated 1 Generates an interrupt when IDSR DIQ 1 EIE 5 0 Error Interrupt Enable When set enables the port write error interrupt when a transfer erro...

Page 834: ...hen this bit is set Also if a valid entry pointed to by the dequeue address pointers has not been serviced within the configured maximum interval this bit is set This bit is cleared if the above conditions are not met or the doorbell controller is disabled Read only 15 8 0 Reserved Write to zero for future compatibility TE 7 0 Transaction Error Set when an internal error occurs during the doorbell...

Page 835: ...e enqueue and dequeue pointers are equal after the processor increments the IDQDPAR the queue is empty and all outstanding doorbells have been processed QE 1 1 Queue Empty If the queue is empty then this bit is set This bit will also be set if the doorbell controller is disabled Read only DIQI 0 0 Doorbell In Queue Interrupt If DIQ is set and IDMR DIQIE is set the controller sets this bit and gene...

Page 836: ...ger full If the IDMR QFIE bit is set then the IDSR QFI is set and the interrupt is generated If the enqueue and dequeue pointers were the same before receiving the doorbell the queue has changed from empty to not empty When the number of doorbells received matches the configured threshold the IDSR DIQ bit is set If the IDMR DIQIE bit is set then the IDSR DIQI bit is also set and the inbound doorbe...

Page 837: ...IRIR Inbound Doorbell Maximum Interrupt Report Offset 0x13478 Interval Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MIRI TYPE R W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIRI TYPE R W R RESET 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Table 16 128 IDMIRIR Field Descriptions Bits Name Description MIRI 31 8 0xFFFFFF Maximum Interrupt Report Interval Maxim...

Page 838: ... the controller has written the port write data payload into memory No interrupt is generated if this if this bit is cleared For proper operation this field should be modified only when the port write controller is not enabled 7 6 0 Reserved Write to zero for future compatibility EIE 5 0 Error Interrupt Enable When set enables a port write error interrupt when a transfer error IPW0SR TE event occu...

Page 839: ...s disabled Read only 19 16 0 Reserved Write to zero for future compatibility TE 15 0 Transaction Error Set when an internal error condition occurs during the port write operation Write a value of 1 to TE to clear it This bit should be modified only when the port write controller is not enabled 6 5 0 Reserved Write to zero for future compatibility QFI 4 0 Queue Full Interrupt If the queue is full a...

Page 840: ... Queue Base Address Register Offset 134EC Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PWQBA TYPE R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWQBA TYPE R W R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 131 IPWQBAR Field Descriptions Bits Reset Description PWQBA 31 6 0 Port Write Queue Base Address Contains the address of the port write data payloa...

Page 841: ...ess space independent from the DSP cores Figure 17 1 shows the block diagram of the dedicated DMA controller Figure 17 1 RapidIO Interface Dedicated DMA Controller Block Diagram CHN 0 CHN 1 CHN 2 CHN 3 Arbitration and Bandwidth Control Source Controls Destination Controls Address Address Address Controls Tenure Data Controls Tenure Serial RapidIO Controller Data Interface Dedicated DMA Controller ...

Page 842: ...dwidth channels accessible by local and remote masters Basic DMA operation modes direct simple chaining Extended DMA operation modes advanced chaining and stride capability Cascading descriptor chains Misaligned transfers Programmable bandwidth control between channels Three priority levels supported for source and destination transactions Interrupt on error and completed segment list or link An A...

Page 843: ... Channel abort capability The software can abort a previously initiated transfer by setting the bit MRn CA The DMA controller terminates all outstanding transfers initiated by the channel without generating any errors before entering an idle state Refer to Section 17 2 Functional Description for details on these modes Figure 17 2 shows the general DMA operational flow chart Figure 17 2 DMA Operati...

Page 844: ...h of the shared resources as specified by the bandwidth control value After the channel uses its allotted bandwidth the arbiter grants the next channel access to the shared resources The arbitration is round robin between the channels This feature is also used to implement the external control pause feature If the external control start and pause are enabled in the MRn the channel enters a paused ...

Page 845: ...red by the DMA controller after the transfer is finished or if the transfer is aborted MRn CA transitions from a 0 to 1 or if a transfer error occurs 7 End of segment interrupt is generated if MRn EOSIE is set 17 2 1 1 2 Basic Direct Single Write Start Mode In basic direct single write start mode the DMA controller does not read descriptors from memory but instead uses the current parameters progr...

Page 846: ...nt After the current segment is finished the DMA controller reads the next link descriptor from memory and begins another DMA transfer The transfer is finished if the current link descriptor is the last one in memory or if an error condition occurs The sequence of events to start and complete a transfer in chaining mode is as follows 1 Build link descriptor segments in memory 2 Poll the channel st...

Page 847: ... extended DMA mode also operates in chaining and direct mode It offers additional capability over the basic mode by supporting striding and a more flexible descriptor structure This additional functionality also requires a new and more complex programming model The extended DMA mode is activated by setting MRn XFE 17 2 1 1 6 Extended Direct Mode Extended direct mode has the same functionality as b...

Page 848: ... MRn CTM to indicate chaining mode MRn XFE must be set to indicate extended DMA mode Other control parameters may also be initialized in the mode register 5 Clear then set the mode register channel start bit MRn CS to start the DMA transfer 6 SRn CB is set by the DMA controller to indicate the DMA transfer is in progress 7 SRn CB is automatically cleared by the DMA controller after finishing the t...

Page 849: ...ontinue bit If EOLND or EOLSD is still set for their respective modes the DMA controller remains in the idle state If EOLND or EOLSD is not set the DMA controller continues the transfer by refetching the new descriptor If CC is set by software while the channel is not busy with a transfer the DMA controller refetches the last link descriptor in basic mode or the last list descriptor in extended mo...

Page 850: ...lowing the next channel to use the shared data transfer hardware This promotes equitable bandwidth allocation between channels However if only one channel is busy hardware overrides the specified bandwidth control size value The DMA controller allows a channel to transfer up to 1 Kbyte at a time when no other channel is active 17 2 1 5 Channel State Table 17 2 defines the state of a channel based ...

Page 851: ...he DMA can be used to achieve data transfers across the entire memory map 17 2 3 DMA Errors On a transfer error uncorrectable ECC errors on memory accesses parity errors on local bus or PCI address mapping errors for example the DMA halts by setting SRn TE and generates an interrupt if MRn EIE is set On a programming error the DMA sets SRn PE and generates an interrupt if MRn EIE is set The DMA co...

Page 852: ...mory Software initializes the current list descriptor address register to point to the first list descriptor in memory The DMA controller traverses through the descriptor lists until the last link descriptor is met as shown in For each link descriptor in the chain the DMA controller starts a new DMA transfer with the control parameters specified by that descriptor Table 17 3 summarizes the DMA lis...

Page 853: ... descriptor in memory After the DMA controller reads the link descriptor from memory this field is loaded into the extended next link descriptor address registers Next link descriptor address Points to the next link descriptor in memory After the DMA controller reads the link descriptor from memory this field is loaded into the next link descriptor address registers Byte count Contains the number ...

Page 854: ...to a reserved transaction interface the source target defaults to local address space Note See Section 17 3 1 Local Access Window Base Address Registers 0 9 LAWBAR 0 9 on page 17 17 and Section 17 3 2 Local Access Window Attributes Registers 0 9 LAWAR 0 9 on page 17 18 for details Offset Field 0x00 Source Attributes 0x04 Source Address 0x08 Destination Attributes 0x0c Destination Address 0x10 Rese...

Page 855: ... source address must be aligned to a size specified by SAHTS If MRn DAHE is set the destination interface transfer size capability must be greater than or equal to MRn DAHTS The destination address must be aligned to the size specified by DAHTS Destination striding is not supported if MRn DAHE is set and source striding is not supported if MRn SAHE is set If the DMA is programmed to send SWRITEs o...

Page 856: ...3 page 17 26 DMA 0 3 Source Attributes Registers SATR 0 3 page 17 27 DMA 0 3 Source Address Registers SAR 0 3 page 17 29 DMA 0 3 Destination Attributes Registers DATR 0 3 page 17 30 DMA 0 3 Destination Address Registers DAR 0 3 page 17 32 DMA 0 3 Byte Count Registers BCR 0 3 page 17 33 DMA 0 3 Next Link Descriptor Extended Address Registers ENLNDAR 0 3 page 17 34 DMA 0 3 Next Link Descriptor Addre...

Page 857: ...R3 Offset 0x1C68 LAWBAR4 Offset 0x1C88 LAWBAR5 Offset 0x1CA8 LAWBAR6 Offset 0x1CC8 LAWBAR7 Offset 0x1CE8 LAWBAR8 Offset 0x1D08 LAWBAR9 Offset 0x1D28 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 5 LAWBARx Field Descriptions Bits Reset Descri...

Page 858: ...W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 6 LAWARx Field Descriptions Bits Reset Description Settings EN 31 0 Enable Enables disables the local access window LAW and all other LAWAR and LAWBAR fields When the LAW is enabled the LAWAR and LAWBAR fields combine to define the address range for this ...

Page 859: ...2 SIZE 1 The minimum size is 4K The maximum size is 64G 001011 4K 001100 8K 001101 16K 001110 32K 001111 64K 010000 128K 010001 256K 010010 512K 010011 1M 010100 2M 010101 4M 010110 8M 010111 16M 011000 32M 011001 64M 011010 128M 011011 256M 011100 512M 011101 1G 011110 2G 011111 4G 100000 8G 100001 16G 100010 32G 100011 64G All others reserved Table 17 6 LAWARx Field Descriptions Continued Bits R...

Page 860: ...e channels are executing transfers concurrently this value determines how many bytes a channel can transfer before the DMA controller shifts to the next channel If a single channel is executing this value determines how many bytes to transfer before pausing the channel after pausing a new assertion of DREQ resumes channel operation 0000 1 byte 0001 2 bytes 0010 4 bytes 0011 8 bytes 0100 16 bytes 0...

Page 861: ...ning mode CDSM SWSM 0 0 Normal operation 1 A write to the destination address register sets MR CS to initiate a DMA transfer CDSM SWSM 1 0 Normal operation 1 A write to the source address register sets MR CS to initiate a DMA transfer EOSIE 9 0 End of Segments interrupt Enable When set generates an interrupt to indicate the completion of a data transfer Note When set the value of this bit override...

Page 862: ...er and clear CB The channel then remains idle until a new transfer is programmed 0 No effect 1 Abort current transfer CTM 2 0 Channel Transfer Mode When set configures the controller in direct mode which means that software must place all the required parameters into the necessary registers to start the DMA transfer 0 Chaining mode 1 Direct mode CC 1 0 Channel Continue chaining mode only When set ...

Page 863: ...is bit to clear it 0 No error during the DMA transfer 1 Error condition during the DMA transfer 6 0 Reserved Write to zero for future compatibility CH 5 0 Channel Halted Indicates whether the transfer is halted Attempts to halt a channel that is idle have no effect If the bit is set the channel was successfully halted by software and can be restarted 0 Channel is not halted 1 DMA successfully halt...

Page 864: ...f MR EOSIE is set then this bit is set and an interrupt is generated Note Write a 1 to this bit to clear it 0 No end of segment interrupt 1 End of segment interrupt EOLSI 0 0 End of List Interrupt After transferring the last block of data in the last list descriptor if MR EOLSIE is set then this bit is set and an interrupt is generated Note Write a 1 to this bit to clear it 0 No end of list interr...

Page 865: ...e is not enabled all DMA transfers are complete and the DMA controller halts If extended chaining mode is enabled the DMA controller examines the state of the EOLSD bit in the next list descriptor address register NLSDAR If EOLSD is clear the controller loads the contents of the ENLSDAR into the Current List Descriptor Extended Address Register ECLSDAR and the contents of the NLSDAR into the CLSDA...

Page 866: ...If EOLSD is set all DMA transfers are complete and the DMA controller halts Table 17 10 describes the CLNDAR fields CLNDAR0 Current Link Descriptor Address Registers 0 3 Offset 0x10C CLNDAR1 Offset 0x18C CLNDAR2 Offset 0x20C CLNDAR3 Offset 0x28C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLNDA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLNDA E...

Page 867: ...n address Table 17 11 describes the fields of the SATR SATR0 Source Attributes Registers 0 3 Offset 0x110 SATR1 Offset 0x190 SATR2 Offset 0x210 SATR3 Offset 0x290 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SBPATMU STFLOWLVL SPCIORDER SSME STRANSINT SREADTTYPE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ESAD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 868: ...tor if MR EOLSIE is set then this bit is set and an interrupt is generated Note This bit is ignored unless SBPATMU is set 1 and the transaction is to the RapidIO interface 1100 RapidIO interface 1111 Local access memory All other values are reserved SREADTTYPE 19 16 0 DMA Source Transaction Type Specifies the source transaction type Note Writing a reserved value to this field causes a programming ...

Page 869: ...0 3 Offset 0x114 SAR1 Offset 0x194 SAR2 Offset 0x214 SAR3 Offset 0x294 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Local SAD RapidIO Source HOP_COUNT CONFIG_OFFSET Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Local SAD RapidIO Source CONFIG_OFFSET Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 12 SAR Field Descriptions Bits Reset Descrip...

Page 870: ...local address space category Table 17 13 describes the fields of the DATR DATR0 Destination Attributes Registers 0 3 Offset 0x118 DATR1 Offset 0x198 DATR2 Offset 0x218 DATR3 Offset 0x298 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBPATMU DTFLOWLVL DPCIORDER DSME DTRANSINT DWRITETTYPE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EDAD R W Reset 0 ...

Page 871: ... this bit is set and an interrupt is generated Note This bit is ignored unless DBPATMU is set 1 and the transaction is to the RapidIO interface 1100 RapidIO interface 1111 Local access memory All other values are reserved DWRITETTYPE 19 16 0 DMA Destination Transaction Type Specifies the destination transaction type Note Writing a reserved value to this field causes a programming error to be detec...

Page 872: ... Registers 0 3 Offset 0x11C DAR1 Offset 0x19C DAR2 Offset 0x21C DAR3 Offset 0x29C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Local DAD RapidIO Dest HOP_COUNT CONFIG_OFFSET Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Local DAD RapidIO Dest CONFIG_OFFSET Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 14 DAR Field Descriptions Bits Reset ...

Page 873: ...BCR2 Offset 0x220 BCR3 Offset 0x2A0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BC Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BC R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 15 BCR Field Descriptions Bits Reset Description 31 26 0 Reserved Write to zero for future compatibility BC 25 0 0 Byte Count Contains the number of bytes to transfer...

Page 874: ...complete and the DMA controller halts If extended chaining mode is enabled the DMA controller examines the state of the EOLSD bit in the next list descriptor address register NLSDAR If EOLSD is clear the controller loads the contents of the ENLSDAR into the ECLSDAR and the contents of the NLSDAR into the CLSDAR and reads the new list descriptor from memory If EOLSD is set all DMA transfers are com...

Page 875: ... controller halts Table 17 17 describes the NLNDAR fields NLNDAR0 Next Link Descriptor Address Registers 0 3 Offset 0x128 NLNDAR1 Offset 0x1A8 NLNDAR2 Offset 0x228 NLNDAR3 Offset 0x2A8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NLNDA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NLNDA NDEOSIE EOLND Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T...

Page 876: ...the last link of the current list is finished all DMA transfers are complete Table 17 18 describes the ECLSDAR fields EOLND 0 0 End of Links Descriptor Indicates whether the descriptor is the last descriptor in memory for this list Note This bit is ignored in direct mode 0 Not the last descriptor for this list 1 Last descriptor for this list ECLSDAR0 Extended Current List Descriptor Address Regist...

Page 877: ...ent list is finished all DMA transfers are complete Table 17 19 describes the CLSDAR fields CLSDAR0 Current List Descriptor Address Registers 0 3 Offset 0x134 CLSDAR1 Offset 0x1B4 CLSDAR2 Offset 0x234 CLSDAR3 Offset 0x2B4 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLSDA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLSDA Type R W Reset 0 0 0 0 0 ...

Page 878: ...es to the internal RapidIO address space Table 17 20 describes the ENLSDAR fields ENLSDAR0 Extended Next List Descriptor Address Registers 0 3 Offset 0x138 ENLSDAR1 Offset 0x1B8 ENLSDAR2 Offset 0x238 ENLSDAR3 Offset 0x2B8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENLSDA Type R W Reset 0 0 0 0 0 0 0 0...

Page 879: ...0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NLSDA EOLSD Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 21 NLSDAR Field Descriptions Bits Reset Description Setting NLSDA 31 5 0 Next List Descriptor Address Holds the next list descriptor address of the buffer descriptor in memory The descriptor must be 32 byte aligned Note This field is used for all transfers For RapidIO transactions ...

Page 880: ...fields SSR0 Source Stride Registers 0 3 Offset 0x140 SSR1 Offset 0x1C0 SSR2 Offset 0x240 SSR3 Offset 0x2C0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS SSD Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 22 SSR Field Descriptions Bits Reset Description 31 24 0 Reserved Write to zero for ...

Page 881: ...lds DSR0 Destination Stride Registers 0 3 Offset 0x144 DSR1 Offset 0x1C4 DSR2 Offset 0x244 DSR3 Offset 0x2C4 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DSS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSS DSD Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 23 DSR Field Descriptions Bits Reset Description 31 24 0 Reserved Write to zero fo...

Page 882: ...ing Error Detected Indicates whether a programming error was detected 0 Normal operation 1 Programming error detected EOLNI0 27 0 Channel 0 End of Links Interrupt Indicates whether an end of links interrupt occurred 0 Normal operation 1 End of links interrupt occurred CB0 26 0 Channel 0 Busy Indicates whether the channel is busy 0 Channel not busy 1 Channel busy EOSI0 25 0 Channel 0 End of Segment...

Page 883: ...busy EOSI2 9 0 Channel 2 End of Segment Interrupt Indicates whether an end of segment interrupt occurred 0 Normal operation 1 End of segment interrupt occurred EOLSI2 8 0 Channel 2 End of Lists Direct Interrupt Indicates whether an end of lists direct interrupt occurred 0 Normal operation 1 End of list direct interrupt occurred TE3 7 0 Channel 3 Transfer Error Indicates whether a transfer error oc...

Page 884: ...MSC8144E Reference Manual Rev 3 17 44 Freescale Semiconductor RapidIO Interface Dedicated DMA Controller ...

Page 885: ...s Multithreading operation Serial numbers SNUMs Instruction RAM IRAM Serial DMA controller Clocking Signal multiplexing Baud rate generation Dedicated interrupt controller Three programmable Unified Communication Controllers UCCs two of which provides dedicated support for an Ethernet controller for MII RMII SMII RGMII SGMII interfaces and one of which provides dedicated support for an ATM control...

Page 886: ...n be programmed to use either an external or internal source The rate of these clocks can be up to one half of the QUICC Engine subsystem clock frequency However the ability of an interface to support a sustained bit stream depends on the protocol settings and other factors Figure 18 1 QUICC Engine Subsystem Architectural Block Diagram UCC1 UCC3 UCC5 SPI1 Communication Interfaces 32 Bit RISC Multi...

Page 887: ...t it is ready for the next command Subsequent commands to the CECR can be given only after FLG is clear The software reset command may be issued by setting RST even if the FLG bit is set The CECR rarely needs to be accessed For example to terminate the transmission of a frame without waiting until the end a STOP TX command is issued through the CECR The worst case command execution latency is 200 ...

Page 888: ... and RxBDs rather than the parameter RAM However if the parameter RAM is accessed note the following You can read the parameter RAM at any time You can write to the Tx parameter RAM only when the transmitter is disabled that is after a STOP TRANSMIT command or after the buffer frame finishes transmitting after a GRACEFUL STOP TRANSMIT command and before a RESTART TRANSMIT command You can write to ...

Page 889: ...at use the following convention BD bd_cstat bit The structural elements of a buffer descriptor are defined as follows Status and control The 16 bit value at offset 0x0 which contains status and control bits that control and report status information on the data transfer The RISC processor updates the status bits after the buffer is sent or received Only this field differs for each protocol Refer t...

Page 890: ...an be even or odd 18 2 5 Multithreading The Ethernet Controllers are able to processes frames or cells at high bit rates gigabit Ethernet and above OC 3 nominal rates In order to achieve these bit rates the UCC receiver and the UCC transmitter are able to process multiple frames cells simultaneously at any given time This is implemented with the multithreading mechanism Each thread processes a dif...

Page 891: ...0x09 0x49 0x89 Thread1 0xC9 Thread9 0x0C Thread18 0x4C 0x8C 0xCC 0x0D Thread19 0x4D 0x8D 0xCD 0x10 Reserved 0x50 Reserved 0x90 Reserved 0xD0 0x11 Reserved 0x51 Reserved 0x91 Reserved 0xD1 0x14 Thread20 0x54 0x94 0xD4 0x15 Thread21 0x55 0x95 0xD5 0x18 0x58 0x98 Thread2 0xD8 Thread10 0x19 0x59 0x99 Thread3 0xD9 Thread11 0x1C Thread22 0x5C 0x9C 0xDC 0x1D Thread23 0x5D 0x9D 0xDD 0x20 UCC3 TX 0x60 Rese...

Page 892: ... QUICC Engine subsystem implements two dedicated virtual SDMA channels for each peripheral one for the receiver and one for the transmitter Additional virtual channels are available for general purpose accesses 18 3 1 Data Paths Figure 18 4 is a simplified block diagram that shows the data paths in the MSC8144E The MSC8144E may be implemented with one DDR bus 32 or 64 bit data The CLASS is respons...

Page 893: ...e DSP core depending on how it is programmed may read the SDMA address register SDTA to determine the address at which the bus error occurred and the SDMA SNUM register SDTM to determine which peripheral or thread was being serviced by the SDMA virtual channel See Table 18 3 for the list of SNUMs The SDTA and the SDTM registers store information related to accesses to the MBus These two registers ...

Page 894: ...DMA is in normal state it requests the bus at priority level programmed by the user in the SDMR EBPR bit field When the SDMA is in emergency state it requests the bus at the highest priority level that the CLASS supports the QUICC Engine subsystem is assigned an arbitration weight through a field in GCR11 see Section 8 2 27 General Control Register 11 GCR11 on page 8 42 for details SDTR and SDHY p...

Page 895: ...ammable multiplexing system to route the various clocks used to transfer data through the external interfaces Depending on the application and interface used these signals can be supplied externally or taken from the internal programmable baud rate generators The following subsections describe the multiplexing unit and the internal baud rate generators 18 4 1 Multiplexer Logic The QUICC Engine sub...

Page 896: ...18 4 and Table 18 5 The bank of clocks selection logic applies an available clock to a peripheral that requires a clock Because the peripheral is not directly connected to a specific clock source peripherals can share the same clock There are two main advantages to the bank of clocks approach First a peripheral is not forced to choose a serial device clock from a predefined input or BRG Second per...

Page 897: ...ck External CLK GE1_RX_CLK GE1_TX_CLK GE2_RX_ER GE2_RX_CLK UTP_RCLK UTP_TCLK UTP_IR UCC1 Rx V UCC1 Tx V UCC3 Rx V UCC3 Tx V UPC Rx V UPC Tx V UPC internal rate V Time Stamp 1 V V Time Stamp 2 V V Bank of Clocks Selection Logic GE1_TX_CLK GE1_RX_CLK Partially filled cross switch logic programmed in the multiplex UCC1 Tx Rx UCC5 Tx Rx UPC Tx Rx Time stamps 1 2 and QUICC Engine timer clocks IR UCC3 T...

Page 898: ...18 14 Freescale Semiconductor QUICC Engine Subsystem Table 18 5 Clock Source Options Internal Clock Generators Clock BRG Number 5 6 7 8 UCC1 Rx V UCC1 Tx V UCC3 Rx V UCC3 Tx V UPC Rx V UPC Tx V UPC internal rate is the UPC1 Tx clock V ...

Page 899: ...e combined source clock divide factor can be changed on the fly except when changing to or from a CD value of 1 2 or 3 For these values disable the BRG and reset it before you program the new value In addition you should not make two changes within two source clock periods If the BRG divides the clock by an even value the transitions of BRGOn always occur on the rising edge of the source clock If ...

Page 900: ...the categories and QUICC Engine subsystem interrupts that are sent to the DSP core Table 18 6 QUICC Engine Subsystem Core Interrupts Category Interrupt Global Interrupts QUICC Engine subsystem DRAM ECC ERROR QUICC Engine subsystem IMEM ECC ERROR QUICC Engine subsystem Interrupt High QUICC Engine subsystem Interrupt Low UCC1 SMII Interrupt UCC3 SMII Interrupt ...

Page 901: ...CC3 RX1 UCC3 RX2 UCC3 RX3 UCC3 RX4 UCC3 RX5 UCC3 RX6 UCC3 RX7 UCC3 TX0 UCC3 TX1 UCC3 TX2 UCC3 TX3 UCC3 TX4 UCC3 TX5 UCC3 TX6 UCC3 TX7 UCC5 ATM Interrupts Global buffer pool busy Global interrupt 0 Global interrupt 1 Global interrupt 2 Global interrupt 3 Global red line Interrupt queue 0 overflow Interrupt queue 1 overflow Interrupt queue 2 overflow Interrupt queue 3 overflow Transmit internal rate...

Page 902: ...terrupt outputs QUICC Engine Subsystem High and QUICC Engine Subsystem Low In addition to the QUICC Engine Subsystem High and Low line each UCC has dedicated interrupts for some of its event The Ethernet controllers UCC1 or UCC3 have 17 interrupts each One interrupt is an OR of all events Each Ethernet controller has also eight RX and eight TX queue interrupts UCC3 Has only thirteen ATM dedicated ...

Page 903: ...O buffers Echo and local loopback modes for testing The UCC block diagram is shown in Figure 18 9 High speed protocols require large FIFO depth Sufficient FIFO size is important for increasing the QUICC Engine subsystem performance by eliminating overrun and underrun bottlenecks Each protocol has an optimized FIFO size that depends not only on the bit rate but also on other parameters such as pack...

Page 904: ...hrough the QUICC Engine subsystem Each controller supports several standard MAC PHY interfaces to connect to an external Ethernet transceiver Supported interfaces include 10 100 Mbps MII interface Ethernet 1 only 1000 Mbps RGMII interface 10 100 Mbps RMII interface 10 100 Mbps SMII interface 1000 Mbps SGMII interface The media independent interface MII was developed first and used four data lines ...

Page 905: ...fication makes use of both the positive and negative edges of the clock Because of this meeting the RGMII specification requires careful attention to timing and delays A second protocol that uses an even lower pin count was developed by Cisco Systems The Serial GMH Specification defines a serial gigabit interface for Ethernet The specification is available from the Cisco website at ftp ftp eng cis...

Page 906: ...ansceiver 10 100 Mbps MII interface IEEE 802 3 2002 standard 1000 Mbps RGMII interface 10 100 RMII interface 10 100 SMII interface The SMII interface is supported by the MIIGSK The MIIGSK controller also supports a SYNC_IN signal 1000 Mbps SGMII interface G MII MAC Layer Host interface TBI RMON Counters Transmit Data FIFO Receive Data FIFO Peripheral Bus Clocks Generator MIIGSK RGMII SerDes MII RM...

Page 907: ...l MII interface The SMII can operate as a MAC to PHY or a MAC to MAC connection A MAC to PHY conveys complete MII information between a 10 100 PHY and MAC using two signals per port and generates the output SYNC signal to allow a MAC to PHY connection The SMII reference clock generates both transmit and receive clocks for the MII interface clocks For a MAC to MAC connection the SMII interface uses...

Page 908: ... signal multiplexing so that the specified signals are made available for use See Chapter 3 External Signals Chapter 5 Reset Chapter 8 General Configuration Registers and Chapter 22 GPIO for programming details Note The MSC8144E allows adjustment of the transmission delays for the Ethernet signal lines except SGMII using GCR4 Recommended settings are listed in the MSC8144E data sheet Guidelines fo...

Page 909: ...RGMII Rising edge receive data bits 0 3 RGMII Falling edge receive data bits 4 7 RMII Receive data bits 1 0 SMII Receive data bit 0 Input Input Input Input Input RX_ER MII Receive error RMII Receive error RGMII SMII Not used Input Input SRIO_REF_CLK SRIO_REF_CLK SGMII Clock MII RMII SMII RGMII Not used Input GEn_SGMII_TX GEn_SGMII_TX SGMII Transmit data MII RMII SMII RGMII Not used Output GEn_SGMI...

Page 910: ..._EN MII Transmit data enable RMII Transmit data enable RGMII Rising edge transmit data enable RGMII Falling edge transmit error RGMII SMII Not used Output Output Output Output TX_ER MII Transmit error RMII RGMII SMII Not used Output Table 18 7 Signal Properties Continued Name Function I O ...

Page 911: ...ith a PHY The speed of operation is determined by the TX_CLK and RX_CLK pins which are driven by the transceiver The bit rate of the transceiver is determined either by auto negotiation or by software via the serial management interface MDC MDIO pins to the transceiver This mode is only supported by Ethernet controller 1 Figure 18 11 MII MAC PHY Interface TX_ER TX_EN TXD 0 3 TX_CLK RX_ER RX_DV RXD...

Page 912: ..._EN TX_ER and TXD signals COL I 1 Collision Asserted when a collision is detected TX_CLK CRS I 1 CRS Asserted when the transmit or receive medium is not idle MDIO I O 1 Management Data Input Output Transfers control signals between the PHY layer and the manger entity MDC MDC I 1 Management Data Clock The MDIO signal clock reference 25 MHz clock RX_ER I 1 Receive Error Asserted by the PHY layer to ...

Page 913: ...rced from the MAC to the PHY or from an external source Figure 18 12 shows the basic components of the RMII including the signals required to make an Ethernet module connection with a PHY Figure 18 12 RMII MAC PHY Interface TX_ER TX_EN TXD 0 3 TX_CLK RX_ER RX_DV RXD 0 3 RX_CLK Transmitter TXD 0 1 RXD 0 1 TX_EN RX_ER REF_CLK MAC Layer PHY RMII Conversion Conversion CRS_DV MII RMII MII RMII Conversi...

Page 914: ...output SYNC signal generation Select this mode by writing a value of 0b10 to MIIGSK_CFGR IFMODE and selecting the ETHSYNC_IN input by writing a 1 to MIIGSK_SMII_SYNCDIR SYNC_IN and a 0 to MIIGSK_SMII_DYNCDIR SYNC The operating mode is determined by the Frequency Control bit MIIGSK_CFGR FRCONT the default value 0 selects 100 Mbps operation Table 18 9 RMII Signals Consortium Name I O Size Function R...

Page 915: ... 18 7 5 1 Reduced Gigabit Media Independent Interface RGMII Signals The RGMII is an alternative to the IEEE Std 802 3u MII the IEEE Std 802 3z GMII and the TBI It reduces the number of signal pins that connect the MAC and PHY from a maximum of 26 pins GMII to 13 pins GTX_CLK included The data paths and all associated control signals are reduced control signals are multiplexed and both edges of the...

Page 916: ..._ER on clock negative edge TXC Tx Data O 4 Transmit Data TXD 0 3 on clock positive edge TXD 4 7 on clock negative edge TXC RX_CTL O 1 Receive Control RX_DV on clock positive edge RX_ER on clock negative edge RXC Rx Data I 4 Receive Data RXD 0 3 on clock posedge RXD 4 7 on clock negedge RXC MDIO I O 1 Management Data I O Transfers control signals between the PHY layer and the manager entity MDC Tx ...

Page 917: ...s providing signal integrity while minimizing system noise Therefore each data and clock signal path uses two physical signal lines the differential pair Table 18 11 lists the SGMII signals MDC I 1 Management Data Clock The MDIO signal clock reference 25 MHz clock RX_CLK I 1 Continuous Receive Reference Clock 125 MHz Table 18 11 SGMII Signals Signal Name I O Size Function Reference Clock SRIO_REF_...

Page 918: ...configure the UEC to suppress the preamble When enabled the length of MII management frames are reduced from 64 to 32 clocks This effectively doubles the efficiency of the interface 18 7 7 Ethernet Controller Initialization After the Ethernet Controller completes the reset sequence software must initialize certain UEC registers and the required parameters in the parameter RAM Based on system requi...

Page 919: ...ICC Engine subsystem supports the following ATM applications ATM line card controllers ATM to WAN interworking frame relay T1 E1 circuit emulation Residential broadband network interface units NIU ATM to Ethernet High performance ATM network interface cards NIC Bridges and routers with ATM interface 18 8 1 Background Asynchronous transfer mode ATM was developed as an international standard to supp...

Page 920: ...al links that implements a virtual connection is chosen when the connection is established For a given physical link each connection is assigned a unique connection identifier The connection identifier is placed in the header of each cell by the transmitting equipment and is used by the receiving equipment to route the cell to the next physical link on the connection path All cells belonging to a ...

Page 921: ...mming ATM operations 18 8 3 UTOPIA Physical Interfaces The UPC external signal descriptions are divided into UTOPIA mode and POS mode signal groups There are several bus configurations depending on the implemented protocol UTOPIA POS the polling method number of devices in the UTOPIA POS configuration and the data bus width For example one UTOPIA device configuration requires a total of 36 I O por...

Page 922: ...ere are two UTOPIA level 2 bus configurations depending on the data bus width For example UTOPIA device configuration requires a total of 36 I O ports for 8 bit mode and 52 bits in 16 bit mode Both configuration use the same number of control signals only the data signal lines are different UTOPIA slave signals are shown in Cross Refs Figure 18 18 Framing 2 82 Enable 2 23 Total for 8 bit 36 424 To...

Page 923: ...igure 18 19 Figure 18 19 POS Master Mode Signals See Chapter 3 External Signals for detailed signal descriptions RXDATA 15 0 7 0 RXSOC RXENB RXPRTY RXCLK RXCLAV RXADD 4 0 QUICC Engine TXDATA 15 0 7 0 TXSOC TXENB TXPRTY TXCLK TXCLAV TXADD 4 0 QUICC Engine UPC Tx UPC Rx TDAT 15 0 7 0 TMOD TENB0 TPRTY TFCLK TADD 4 0 QUICC Engine Block RDAT 15 0 7 0 QUICC Engine Block TSOP TEOP TERR STPA PTPA0 DTPA0 R...

Page 924: ... of transmitter and receiver sections an independent baud rate generator and a control unit The transmitter and receiver sections use the same clock which is derived from the SPI baud rate generator in master mode and generated externally in slave mode During an SPI transfer data is sent and received simultaneously The SPI receiver and transmitter are double buffered as shown in Figure 18 21 givin...

Page 925: ...n master mode the SPI sends a message to the slave peripheral which sends back a simultaneous reply A single master device with multiple slaves can use general purpose parallel I O signals to selectively enable slaves as shown in Figure 18 22 To eliminate the multi master error in a single master environment the master SPI_SL input can be forced inactive by selecting SPI_SL for general purpose I O...

Page 926: ...nt or an error occurs The QUICC Engine subsystem then clears TxBD R and RxBD E and issues a maskable interrupt to the interrupt controller When multiple TxBDs are ready TxBD L determines whether the SPI keeps transmitting without SPCOM STR being set again If the current TxBD L is cleared the next TxBD is processed after data from the current buffer is sent Typically there is no delay on SPI_MOSI b...

Page 927: ..._SL remains asserted Note When enabling the SPI or changing parameters in SPI Mode Register like CP CI SPI_SL must remain deasserted for at least 2 QUICC Engine clk 2 clocks afterwards Also if SPI_SL is deasserted between transfers its deassertion time should be at least 2 QUICC Engine clk 2 clocks 18 9 2 SPI in Multi Master Operation The SPI can operate in a multi master environment in which SPI ...

Page 928: ... with more than two masters SPI_SL and SPIE MME It is the responsibility of the software to arbitrate for the SPI bus with token passing will not detect all possible conflicts SPI_SLx signals are implemented in the software with general purpose I O signals SPI_SL1 SPI_SL0 SPI_SL3 SPI_SL2 SPI 3 for example SPI_MISO SPI_MOSI SELOUT0 SPI_SL SPI_CK SELOUT3 SELOUT2 SPI_MISO SPI_MOSI SELOUT0 SPI_SL SPI_...

Page 929: ...slave in SPI_MOSI signal is an output for master devices The dual functionality of these signals allows the SPIs in a multimaster environment to communicate with one another using a common hardware configuration When the SPI is a master SPI_CK is the clock output signal that shifts received data in from SPI_MISO and transmitted data out to SPI_MOSI SPI masters must output a slave select signal to ...

Page 930: ...PI registers with their offsets Note The QUICC Engine registers use a base address of 0xFEE00000 Table 18 14 MSC8144E QUICC Engine Register Summary Register Name Acronym Offset IRAM Registers IRAM Address Register IADD 0x0000 IRAM Data Register IDATA 0x0004 Interrupt Controller Registers QUICC Engine System Interrupt Configuration Register CICR 0x0080 QUICC Engine Interrupt Vector Register CIVEC 0...

Page 931: ...x04EC Baud Rate Generators Baud Rate Generator Configuration Registers 5 BRGCR5 0x0650 Baud Rate Generator Configuration Registers 6 BRGCR6 0x0654 Baud Rate Generator Configuration Registers 7 BRGCR7 0x0658 Baud Rate Generator Configuration Registers 8 BRGCR8 0x065C UCC Registers UCC1 General Mode Register GUMR1 0x2000 UCC1 Protocol Specific Mode Register UPSMR1 0x2004 UCC1 Transmit On Demand Regi...

Page 932: ...ation Address Part 2 Register E1MACSTNADDR2 0x2144 Ethernet 1 MAC Parameter Register UEMPR1 0x2150 Ethernet 1 Ten Bit Interface Physical Address Register UTBIPAR1 0x2154 Ethernet 1 Statistics Control Register UESCR1 0x2158 Ethernet 1 Tx 64 byte Frames E1TX64 0x2180 Ethernet 1 Tx 65 to 127 byte Frames E1TX127 0x2184 Ethernet 1 Tx 128 to 255 byte Frames E1TX255 0x2188 Ethernet 1 Rx 64 byte Frames E1...

Page 933: ... Register E2MACCFG2 0x2304 Ethernet 2 Interframe Gap Register E2PGFG 0x2308 Ethernet 2 Half Duplex Register HAFDUP2 0x230C Ethernet 2 MII Management Configuration Register MIIMCFG2 0x2320 Ethernet 2 MII Management Command Register MIIMCOM2 0x2324 Ethernet 2 MII Management Address Register MIIMADD2 0x2328 Ethernet 2 MII Management Control Register MIIMCON2 0x232C Ethernet 2 MII Management Status Re...

Page 934: ...rames Minimum E2EtherStatsframe64 0x238C Ethernet 2 Rx Frames MINLength E2EtherStatsPkts65 0x2390 Ethernet 2 Rx Frames 128 E2EtherStatsPkts128 0x2394 Ethernet 2 Octet Transmitted OK E2OcTxOK 0x2398 Ethernet 2 Tx Pause Frames E2PausFrTx 0x239C Ethernet 2 Multicast Frame Transmitted OK E2MulCastFrTxOK 0x23A0 Ethernet 2 Broadcast Frames Transmitted OK E2BroadCastFrTxOK 0x23A4 Ethernet 2 Number of Fra...

Page 935: ...ter 2 MIIGSK2_CFGR 0x2A00 MIIGSK Enable Register 2 MIIGSK2_ENR 0x2A08 MIIGSK SMII SYNC Direction Register 2 MIIGSK2_SMII_SYNCDIR 0x2A0C MIIGSK SMII Transmit Inter Frame Bits Register 2 MIIGSK2_TIFBR 0x2A10 MIIGSK SMII Receive Inter Frame Bits Register 2 MIIGSK2_RIFBR 0x2A14 MIIGSK SMII Expected Receive Inter Frame Bits Register 2 MIIGSK2_ERIFBR 0x2A18 MIIGSK Interrupt Event Register 2 MIIGSK2_IEVE...

Page 936: ...R 0x4004 Serial DMA Threshold Register SDTR 0x4008 Serial DMA Hysteresis Register SDHY 0x4010 Serial DMA Transfer Address Register SDTA 0x4018 Serial DMA Transfer Channel Number Register SDTM 0x4020 Serial DMA Address Qualify Register SDAQR 0x4038 Serial DMA Address Qualify Mask Register SDAQMR 0x403C Serial DMA Temporary Buffer Base in Multi User RAM Value SDEBCR 0x4044 Table 18 14 MSC8144E QUICC...

Page 937: ... and independent TDM modules each supporting 256 bidirectional channels 256 transmit and 256 receive channels running at up to 62 5 Mbps with 2 4 8 and 16 bit word size The TDM bus connects gluelessly to most T1 E1 framers as well as to common buses such as the ST Bus Each TDM module operates in independent or shared mode when receiving or transmitting data In independent mode there are different ...

Page 938: ...nc signals between the TDM modules and the MSC8144E signal lines The TDM may be configured by all four SC3400 cores see Figure 19 1 as well as by an external host Data is received and transmitted from the TDM modules to the channel buffers through the internal MBus Figure 19 2 shows the TDM block diagram and the receive and transmit data flows The dashed line depicts the transmit data flow from th...

Page 939: ...tdm7_tclk tdm7_rclk 4 4 6 _ TDM7TCLK tdm7_tsync TDM 7 3 Rx error int0 Rxthreshold1 int0 Rxthreshold2 int0 1 1 2 Rx error int1 Rx threshold1 int1 Rx threshold2 int1 2 Rx error int2 Rx threshold1 int2 Rx threshold2 int2 3 4 Rx error int7 Rx threshold1 int7 Rx threshold2 int7 4 TDM 1 TDM 2 tdm1_rdata_a d tdm1_rsync tdm1_rclk tdm1_tdata_a d tdm1_tsync tdm1_tclk TDM 0 tdm0_rdata_a d tdm0_rsync tdm0_tda...

Page 940: ...Bus Multiplex tdmx_rdata_a tdmx_rdata_b tdmx_rdata_c tdmx_rdata_d tdmx_rsync tdmx_rclk 64 IP logic Status Registers Control Registers Configuration Registers 32 From I O Matrix To I O Matrix TDM x Machine 32 Notes X is the TDM number 0 7 A m Law Data Conversion 64 64 128 Transmit data out Receive data flow Transmit data flow tdmx_tdata_a tdmx_tdata_b tdmx_tdata_c tdmx_tdata_d tdmx_tsync tdmx_tclk ...

Page 941: ...e network through a framer Figure 19 3 TDM Point to Point Configuration Figure 19 4 TDM Point to Multi Point Configuration TDMxTDAT TDMxTSYN TDMxTCLK TDMxRDAT TDMxRSYN TDMxRCLK TDMxRDAT TDMxRSYN TDMxRCLK TDMxTDAT TDMxTSYN TDMxTCLK On Board Clock Generator On Board Clock Generator MSC8144E MSC8144E TDMxTDAT TDMxTCLK TDMxTSYN TDMxRDAT TDMxRCLK TDMxRSYN From Receiver Clock Generator From transmitter ...

Page 942: ...s for each TDM module is unified and it can be 2 4 8 and 16 bits The receive channel size is determined by the RCS field in the TDMxRFP the transmit channel size is determined by the TCS field in the TDMxTFP refer to page 19 51 When the TDM connects to a T1 framer the RT1 field in the TDMx Receive Frame Parameters Register TDMxRFP see page 19 48 and the TT1 field in the TDMx Transmit Frame Paramet...

Page 943: ...AT receive data Channel 0 Channel 1 Channel 0 Channel 1 Channel0 TDMxTCLK transmit clock TDMxTSYNC transmit sync TDMxTDAT channel 0 channel 1 Channel 2 Channel 3 Channel 0 Receive Frame parameters RNCF 7 0 0x1 2 channels RCS 0x1 2 bits and RT1 0 nonT1 TNCF 7 0 0x3 4 channels TCS 0x3 4 bits and TT1 0 non T1 Transmit Frame parameters Channel size Frame Size TDMxT RCLK TDMxT RSYN TDMxT RDAT FA D0 D1 ...

Page 944: ...ve of all TDM modules share the same sync signal In independent mode connect the transmit shared clock to TDM0TCLK transmit of all TDM modules share the same clock signal Connect the receive shared clock to TDM1TCLK receive of all TDM modules share the same clock signal When the TDMxTIR TSO bit is set to a value of 1 see page 19 46 the sync out signal drives out through TDM0TSYN The configuration ...

Page 945: ... TDM1RSYN Rxdata 3 TDM1RCLK Txdata 2 TDM1TDAT Txdata 3 TDM1TSYN Rxsync common TDM1TCLK Rxclk common TDM2RDAT R2data 0 TDM2RSYN R2sync TDM2RCLK R2clk TDM2TDAT T2data0 TDM2TSYN T2sync TDM2TCLK T2clk TDM7RDAT R7data 0 TDM7RSYN R7sync TDM7RCLK R7clk TDM7TDAT T7data0 TDM7TSYN T7sync TDM7TCLK T7clk RTSAL 3 0 0001 CTS 1 RTSAL 3 0 0001 CTS 1 RTSAL 3 0 0000 CTS 0 RTSAL 3 0 0000 CTS 0 TDM0 TDM1 TDM2 TDM7 TD...

Page 946: ...The transmit and the receive share the Frame Sync FSYN and the Frame Clock FCLK signals The number of receive and the transmit active links can be one or two The direction of the receive links is input and the direction of the transmit links is output When RTSAL 3 2 in the TDMx General Interface Register see page 19 36 equal 0b11 the receive and the transmit are shared as illustrated on the right ...

Page 947: ...ent TDM Module TDMxRDAT TDMxRSYN TDMxRCLK TDMxTDAT TDMxTSYN TDMxTCLK TDMxRDAT TDMxRSYN TDMxRCLK TDMxTDAT TDMxTSYN TDMxTCLK Independent Receive Shared Data x Defines the TDM number TDMxRDAT TDMxRSYN TDMxRCLK TDMxTDAT TDMxTSYN TDMxTCLK and Transmit Shared Clock and Frame Sync TDM Module TDM Module FSYNC frame sync specifies that the receiver and transmitter share the same sync FCLK frame clock speci...

Page 948: ...nc Clock and Data Four Active Links TDMxTCLK FCLK TDMxTSYN FSYN TDMxRDAT RDATA_A Channel N 3 Channel 0 Channel 1 Channel 4 Channel 5 Channel 8 Channel 9 TDMxRSYN RDATA_B Channel N 1 Channel 2 Channel 3 Channel 6 Channel 7 Channel 10 Channel 11 x The TDM number N The number of channels in a TDM frame Channel N 3 Channel 0 Channel 1 Channel 4 Channel 5 Channel 8 Channel 9 Channel N 1 Channel 2 Chann...

Page 949: ...2 5 MHz 19 2 3 TDM Data Structures TDM data structures are stored in transmit and receive local memory as follows TDM receive local memory Received data is stored in 256 8 byte entries located in addresses between 0x0000 0x07FF which is offset from the TDMx receive local memory see Chapter 9 Memory Map This memory contains 1 2 4 8 16 or 32 indexed buffers starting at 0 Each buffer contains multipl...

Page 950: ...bytes of channel 2 are located in four buffers TNB 3 Only 8 receive bytes of channel 2 are located in one buffer RNB 0 Each buffer contains 8 bytes per channel When the TDM transmit local memory is accessed using addresses with 8 byte alignment data is written to the 4 LSB of the memory row Figure 19 16 describes the TDMx local memory after write access of 0x01234567 to address 0x1800 offset from ...

Page 951: ...set then the TDMx TSO bits should be equal for all the TDM modules and they determine whether the sync arrives from the board or is generated by the TDM0 transmitter Configuring the sync out signal involves the parameters listed in Table 19 3 Figure 19 17 TDMx Local Memory Read Example Table 19 3 Parameters in Configuring the Frame Sync TDMxTIR TSO 1 Task Register Control the length of the sync_ou...

Page 952: ... different clock edge is TFSD 1 0 5 Figure 19 18 Sync Length Selection Table 19 4 Transmit and Receive Frame Configuration Control Register Which receive clock edge samples the receive frame sync If RFSE is clear the receive frame sync is sampled on the rising edge of the receive clock TDMxRIR RFSE bit page 19 44 Which transmit clock edge samples the transmit frame sync If TFSE is clear the transm...

Page 953: ...ata and the sync drive sample at the different edges TDE 1 TFSE 0 TFSD 00 Start of the frame 0 5 bit delay data driven out 0 5 bits before the sync is sampled The data and the sync sample with the same edge Two bit delay The data and the sync sample with different edges RDE 1 RFSE 0 RFSD 10 Start of the frame 2 5 bit delay TDMxTCLK TDMxTSYN TDMxTDAT D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 Cha...

Page 954: ... beginning of every frame The frame sync synchronization is necessary when more than one device drives the bus Figure 19 22 shows the state diagram of the frame sync synchronization Figure 19 20 Frame Sync Configuration At T1 Mode Figure 19 21 Frame Sync Polarity TDMxRCLK TDMxRSYN TDMxRDAT D0 D1 D7 D0 D7 FA D6 Start of the Frame No sync delay The data and the sync sample with the same edge RDE 0 R...

Page 955: ...gnized early the state returns to the WAIT state Otherwise the machine transfers to the SYNC state at the last bit of the TDM frame During PRESYNC state data is neither received nor transmitted SYNC 0b10 At least one sync event has appeared exactly where it was expected This state is maintained as long as the sync event continues to appear where expected If a sync is missed or a sync event is reco...

Page 956: ...n state returns to SYNC state If the TDMxTIR TAO bit is clear data is not driven out and TDMxTDAT is tri stated When the transmit sync synchronization is lost the TDMxTER TSE bit see page 19 70 is asserted If the TDMxTIER TSEIE bit see page 19 65 is also set a transmit error interrupt is generated The ISR should clear the TDMxTER TSE bit by writing a 1 to the bit before clearing the related status...

Page 957: ... D0 D1 D2 D3 D4 D5 D6 D7 D0 Channel N Row in Memory Channel N LSB MSB D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 Reverse Data Bit Order RRDO TRDO 1 TDMxCLK receive transmit TDMxDAT receive transmit D0 D1 D2 D3 D4 D5 D6 D7 D0 Channel N Row in Memory Channel N D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 Reverse Data Bit Order RRDO TRDO 0 LSB MSB ...

Page 958: ...uffer Data transmitted from memories mapped on the system I F is temporarily stored in the TDM transmit local memory until it is transferred externally A single data transfer from the system I F to TDM local memory transfers at least 64 bits of data Each channel can store more than 64 bits before it is transmitted externally The TDMxTFP TCDBL field provides an upper boundary on the number of trans...

Page 959: ...d bits essentially occupying double the size When the TDMxTCPRn TCONV field see page 19 63 indicates that a channel is an A law channel the transmitted 13 bits are converted into an 8 bit PCM sample This channel therefore occupies 16 bits 13 bits padded with three zeros at the right per 8 transmit bits essentially occupying double the size When the TDMxTCPRn TCONV field indicates that a channel is...

Page 960: ...DBD The RDBD can be used to show that data is written to the buffer and can be processed The address of a transmit buffer is a function of the following Transmit Global Base Address TDMxTGBA TGBA field page 19 55 Transmit Channel Data Base Address TDMxTCPRn TCDBA field page 19 63 TGBA 16 TCDBA points to the first byte of transmit data buffer n The four lsbs of TCDBA must be 0000 Transmit Data Buff...

Page 961: ... TDMxRGBA 16 Receive Data Buffer Memory Map 8 bytes channel k A μ law active transparent channel transparent channel Receive Data Buffer i RDBS Bytes RDBSx2 Bytes RCPRk RCDBA Transmit Global Base Address TDMxTGBA 16 Transmit Data Buffer channel m A μ law active Bytes TDBS Bytes TDBSx2 RCPRi RCDBA Transmit data buffer l TCPRl TCDBA TCPRm TCDBA 0000 RCDBA RCPRx RGBA RGBA Receive data buffer i base a...

Page 962: ...is level the ISR should clear the TDMxRER RSTE bit by writing a 1 to it If the interrupt is pulse there is no need to clear the status bit When the interrupt is asserted in the EPIC then the SC3400 core can read all the receive buffers up to the byte to which the second threshold TDMxRDBST RDBST points Meanwhile the TDM keeps writing new data to the first part of the buffer The transmit data buffe...

Page 963: ...rupt routine that handles the receive first threshold interrupt should include If TDMxRDBFT RDBFT TDMxRDBS RDBS 0xF then TDMxRDBFT RDBFT 0x0 else if TDMxRDBFT RDBFT TDMxRDBS RDBS 0x7 then TDMxRDBFT RDBFT 0x8 else TDMxRDBFT RDBFT TDMxRDBFT RDBFT 0x10 The interrupt routine that handles the receive second threshold interrupt should include If TDMxRDBST RDBST TDMxRDBS RDBS 0xF then TDMxRDBST RDBST 0x0...

Page 964: ...FP TCS 1 For example if the number of transmit channels that is TDMxTFP TNCF 1 is 32 and the transmit channel size that is TDMxTFP TCS 1 is 8 bits then the number of non transmitted bits is 480 These bits not transmitted are located in the TDM local memory and or in the device level memory M2 M3 DDR and so forth Figure 19 27 describes the transmit data flow in independent data buffers mode TDMxTFP...

Page 965: ...ed Buffer Mode the RRDO bit in the TDMxRIR should be cleared When the transmitter is configured as Unified Buffer Mode the TRDO bit in the TDMxTIR should be cleared 19 2 7 Adaptation Machine Each TDM module has an Adaptation Machine that counts the number of bits between frame SYNCs This module can be used to determine the frame size in bits Figure 19 28 Receive Unified Buffer Mode RUBM 1 TDMxRSYN...

Page 966: ...n Status Register TDMxASR The following steps define how to use the Adaptation Machine 1 Configure the LTS bit to define whether the Adaptation Machine is fed with the Transmit or with the receive frame sync and clock See page 19 57 2 Set the AME bit in the TDMxACR to enable the Adaptation Machine 3 Wait for AMS bit in the TDMxASR to be set to 1 See the TDMx Adaptation Status Register on page 19 7...

Page 967: ... both transmitter and receiver are disabled In addition the TDM registers get the CLASS64 clock only at reset or during an access 19 4 Channel Activation The TACT and RACT bits in the Transmit Receive Channel Parameter n Registers see page 19 62 and page 19 63 are enabled during the receiver transmitter operation to control the channel activation If the TACT RACT bit is clear the channel is not ac...

Page 968: ... receiver receives the same data that is transmitted The frame clock should supply to the TDM and the frame sync can be generated internally or supplied externally The receiver and transmitter share the frame sync frame clock and data links RTSAL 3 2 0b11 The number of data links can be 1 2 or 4 and is determined by the RTSAL 1 0 bits All the receive and transmit frame channels are active The proc...

Page 969: ...clear the receive TDM is disabled but all the registers retain their values except for the TDMx Receive Data Buffers Displacement Register TDMxRDBDR The TDMxTCR TEN bit see page 19 59 enables the transmit part of the TDM module When TDMxTCR TEN is clear the transmit TDM is disabled but all the registers retain their values except for the TDMx Transmit Data Buffers Displacement Register TDMxTDBDR T...

Page 970: ...itted data is indicated in the TNB field of the TDMx Transmitter Number of Buffers Register TDMxTNB Channel C in buffer B is the 8 bytes starting at 256 TNB 1 B C 8 5 Clear the TDMxRER and TDMxTER event registers by writing a value of 0xF to each of them 6 Set the TDMxRCR REN bit and or the TDMxTCR TEN bit 19 7 TDM Programming Model The handshake between the TDM module and the SC3400 core occurs v...

Page 971: ...59 TDMx Receive Data Buffers First Threshold TDMxRDBFT page 19 59 TDMx Transmit Data Buffers First Threshold TDMxTDBFT page 19 60 TDMX Receive Data Buffers Second Threshold TDMxRDBST page 19 61 TDMx Transmit Data Buffers Second Threshold TDMxTDBST page 19 61 TDMx Receive Channel Parameter Register 0 255 TDMxRCPR 0 255 page 19 62 TDMx Transmit Channel Parameter Register 0 255 TDMxTCPR 0 255 page 19...

Page 972: ...DMx interface operation mode TDMxGIR TDMx General Interface Register Offset 0x3FF8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYNC_ MODE CTS RTSAL Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 6 TDMxGIR Bit Descriptions Name Reset Description Settings 31 6 0 Reserved Write to zero for future...

Page 973: ...4 share signals but TDM 5 7 do not share signals with the other TDM modules TDMxCTS 1for 0 x 4 TDMyCTS 0 for 5 y 7 TDM 0 5 share signals but TDM 6 7 do not share signals with the other TDM modules TDMxCTS 1for 0 x 5 TDMyCTS 0 for 6 y 7 TDM 0 6 share signals but TDM 7 do not share signals with the other TDM modules TDMxCTS 1for 0 x 6 TDM7CTS 0 TDM 0 7 share signals TDMxCTS 1for 0 x 7 Table 19 7 on ...

Page 974: ... 2 1 Common Signals for the TDM Modules on page 19 8 Note Unused signals should not be configured as dedicated signals in the PAR 0000 The receive and transmit are independent The TDM receives one data link and transmits one data link 0001 The receive and transmit are independent The TDM receives two data links and transmits two data links valid only if CTS 1 0010 Reserved 0011 Reserved 0100 The r...

Page 975: ...hare the same clock TDM0TCLK Frame sync receive and transmit share the same sync TDM0TSYN Receive data links TDMxRDAT TDMxRSYN Transmit data links TDMxTDAT TDMxRCLK Unused signals TDMyTCLK TDMyTSYN TDMx specifies the TDM number and any one of the shared TDM modules TDMy specifies the TDM number and any one of the shared TDM modules except TDM0 For example if TDM0 and TDM1 share signals the unused ...

Page 976: ...ignal Configuration as a Function of the RTSAL and CTS Fields No C T S RTSAL 3 0 TDMxRDAT TDMxRSYN TDMxRCLK TDMxTDAT TDMxTSYN TDMxTCLK Comments 0 0 0000 receive data RDATA_A receive sync receive clock transmit data TDATA_A transmit sync transmit clock The TDM does not share signals with others TDM modules Independent mode One active data link direction Input Input Input Output Inout Input 1 0 0001...

Page 977: ...ot used frame sync frame clock The TDM does not share signals with other TDM modules Receive and transmit share the sync clock and data signals One full duplex active data link direction Inout Inout Input 9 0 1101 data link DATA_A data link DATA_B not used not used frame sync frame clock The TDM does not share signals with other TDM modules Receive and transmit share the sync clock and data signal...

Page 978: ...Output Inout Input 13 1 0001 receive data RDATA_A receive data RDATA_B transmit data TDATA_B transmit data TDATA_A receive sync transmit sync not used receive clock transmit clock not used The TDM shares receive sync and clock and transmit sync and clock with other TDM modules Independent mode Two active data links direction Input Input Output Output Inout Input 14 1 0010 Reserved 15 1 0011 Reserv...

Page 979: ...e sync not used frame clock not used The TDM shares the frame sync and frame clock with other TDM modules Receive and transmit share the sync clock and data signals One full duplex active data link direction Inout Inout Input 21 1 1101 data link DATA_A data link DATA_B not used not used frame sync not used frame clock not used The TDM share the frame sync and frame clock with other TDM modules Rec...

Page 980: ...3 22 21 20 19 18 17 16 RBOR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Boot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFTL RSTL RFSD RSL RDE RFSE RRDO Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 9 TDMxRIR Bit Descriptions Name Reset Description Settings 31 17 0 Reserved Write to zero for future compatibility RBOR ...

Page 981: ...active on logic 0 RDE 2 0 Receive Data Edge Determines whether the receive data signal is sampled on the rising or falling edge of the receive clock For details see Section 19 2 4 2 0 The receive data signal is sampled on the rising edge of the receive clock 1 The receive data signal is sampled on the falling edge of the receive clock RFSE 1 0 Receive Frame Sync Edge Determines whether the receive...

Page 982: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TBOR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Boot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFTL TSTL TSO TAO SOL SOE TFSD TSL TDE TFSE TRDO Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 11 TDMxTIR Bit Descriptions Name Reset Description Settings 31 17 0 Reserved Writ...

Page 983: ...ompatibility TFSD 5 4 0 Transmit Frame Sync Delay With the TDE and the TFSE bits determines the number of clocks between the transmit sync signal and the first data bit of the transmit frame For examples see Section 19 2 4 2 Refer to Table 19 12 on page 47 Note If the transmit channel size is 2 TCS 0x1 then the TFSD field value can be only 0 or 1 TSL 3 0 Transmit Sync Level Determines the polarity...

Page 984: ...sample and the first data bit of the frame that is driven out 2 The field value is negative because the data is driven out before the transmit frame sync sample TDMxRFP TDMx Receive Frame Parameters Offset 0x3FE0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RNCF Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCDBL RCS RT1 RUBM Type R W Reset 0 0 0 0...

Page 985: ...0xFF 256 received channels Note The even values are reserved 15 11 0 Reserved Write to zero for future compatibility RCDBL 10 8 0 Receive Channel Data Bits Latency Defines the maximum amount of receive channel bits stored in the TDM local memory before they are transferred for processing RCDBL determines the maximum data latency in the following way Maximum data latency RCDBL RCS receive frame dur...

Page 986: ...ffer When RUBM is set the number of active links must be 1 RTSAL 0b0000 or RTSAL 0100 The channel parameters of all active channels are located in the TDMxRCPR0 See page 19 62 For details see Section 19 2 6 4 Note When this bit is set the TDMxRIR RRDO bit should be cleared 0 Each channel is written to a different data buffer in the internal MBus 1 All the channels are written to the same data buff...

Page 987: ...ules One TDM frame contains 2 256 channels Notes 1 TNCF 8 15 number of channels that transmit on one active link number of active data links 1 the number of active data links is specified in the RTSAL field 2 If TCDBL field is cleared the minimum number of channels is limit The minimum transmit number of channels is 128 transmit channel size 2 for example if the transmit channel size is 16 bits th...

Page 988: ... 1 For details see Section 19 2 5 0000 Reserved 0001 The transmitter channel size is 2 bits 0010 Reserved 0011 The transmitter channel size is 4 bits 0100 Reserved 0101 Reserved 0110 Reserved 0111 The transmitter channel size is 8 bits 1000 1110 Reserved 1111 The transmitter channel size is 16 bits TT1 1 0 Transmit T1 Frame Determines whether the TDM transmitter drives a T1 frame or non T1 frame N...

Page 989: ... xxxxx111 The total number of channels must have a granularity of eight TDMxRDBS TDMx Receive Data Buffer Size Offset 0x3FD0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDBS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDBS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 17 TDMxRDBS Bit Descriptions Name Reset Description Settings 31 24 0...

Page 990: ...5 4 3 2 1 0 TDBS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 18 TDMxTDBS Bit Descriptions Name Reset Description Settings 31 24 0 Reserved Write to zero for future compatibility TDBS 23 0 0 Transmit Data Buffers Size Transmit data buffers size equals the transmit data buffer size in bytes minus 1 The buffer size is aligned to 8 bytes so bits 29 31 must be set to 111 For details see Sec...

Page 991: ...et 0x3FB8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGBA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 20 TDMxTGBA Bit Descriptions Name Reset Description 31 16 0 Reserved Write to zero for future compatibility TGBA 15 0 0 Transmit Global Base Address Determines the global base address of t...

Page 992: ... set the PUV using PUV 64 TDMxTFP TCS TDMxTNB TNB See page 19 51 for TDMxTFP details and page 19 69 for TDMxTNB details TDMxRFR TDMx Receive Force Register0x3F18 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 22 TDMxRFR Bit Descriptions Name Rese...

Page 993: ...et Description Settings 31 3 0 Reserved Write to zero for future compatibility PC 2 0 Parity Check Enables the parity check mechanism When the bit is set you can write to TDMxRCPRn 27 24 or TDMxTCPRn 27 24 0 Parity check is disabled 1 Parity check is enabled PIE 1 0 Parity Interrupt Enable Enables disables the parity interrupt 0 Parity interrupt is disabled 1 Parity interrupt is enabled PIL 0 0 Pa...

Page 994: ... or disabled 0 Adaptation machine is disabled 1 Adaptation machine is enabled LTS 0 0 Learn Transmit Sync Determines whether the adaptation machine learns the transmit sync or the receive sync 0 Adaptation machine learn the receive sync 1 Adaptation machine learn the transmit sync TDMxRCR TDMx Receive Control Register Offset 0x3FA8 Reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset...

Page 995: ...can be updated at any time even when the TDMx receiver is enabled For details see Section 19 2 6 3 TDMxTCR TDMx Transmit Control Register Offset 0x3FA0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TEN Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 27 TDMxTCR Bit Descriptions Name Reset...

Page 996: ... 31 24 0 Reserved Write to zero for future compatibility RDBFT 23 0 0 Receive Data Buffer First Threshold Determines the location of the first threshold in the receive data buffers The register value has a granularity of 8 bytes that is the three LSBits are always clear 0x000000 to RDBS 7 TDMxTDBFT TDMx Transmit Data Buffer First Threshold Offset 0x3F90 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 997: ...ta Buffers Displacement Register TDMxTDBDR the Transmit Data Buffers Second Threshold TDMxTDBST 8 then the TSTE bit in the TDMx Transmit Register TDMxTER is set If TDMxRDBST TDMx Receive Data Buffer Second Threshold Offset 0x3F88 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RDBST Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDBST Type R W...

Page 998: ...FP RNCF bit see page 19 48 should be valid when setting the corresponding TDMxRCR REN bit see page 19 58 The TDMxRCPRn registers are implemented using a compiled memory and include support of parity mechanisms that allows detection and correction of one soft error using an interrupt see TDMxPCR on page 19 57 Table 19 31 TDMxTDBST Bit Descriptions Name Reset Description Settings 31 24 0 Reserved Wr...

Page 999: ...NCF bit see page 19 51 should be valid when setting the corresponding TDMxTCR TEN bit see page 19 59 RCONV 30 29 Receive Channel Convert Determines the type of the incoming channel n Transparent A law or μ Law 00 Receive channel n is a transparent channel 01 Receive channel n is a μ Law channel 10 Receive channel n is an A Law channel 11 Reserved 28 Reserved Write to zero for future compatibility ...

Page 1000: ... is a μ Law channel 10 Transmit channel n is an A Law channel 11 Reserved 28 Reserved Write to zero for future compatibility 27 24 These bits are used for parity protection TCDBA 23 0 Transmit Channel Data Buffer Base Address Determines the offset of the transmit data buffer n base address from the Transmit Global Base Address TGBA The TCDBA value should be 16 byte aligned that is the four LSB sho...

Page 1001: ...interrupt is enabled TDMxTIER TDMx Transmit Interrupt Enable Register Offset 0x3F70 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSEIE ULBEETFTEETSTEE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 35 TDMxTIER Bit Descriptions Name Reset Description Settings 31 4 0 Reserved Write to zero for fu...

Page 1002: ...8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASD Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 36 TDMxASDR Bit Descriptions Name Reset Description Settings 31 11 0 Reserved Write to zero for future compatibility ASD 10 0 0 Adaptation Sync Distance Indicate the number of bits between the last two...

Page 1003: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDBD Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 37 TDMxRDBDR Bit Descriptions Name Reset Description Settings 31 24 0 Reserved Write to zero for future compatibility RDBD 23 0 0 Receive Data Buffer Displacement Points to the current displacement of the received data in the data buffers The value is unified to all th...

Page 1004: ... buffers The value is unified to all the transparent channels and is doubled for A μ law channels The register value can range from 0x000000 to the Transmit Data Buffer TDBS 7 TDMxRNB TDMx Receive Number of Buffers Offset 0x3F50 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RNB Type R Reset 0 0 0 0 0 0 0 0...

Page 1005: ... 0 0 0 0 0 0 0 0 0 Table 19 40 TDMxTNB Bit Descriptions Name Reset Description Settings 31 5 0 Reserved Write to zero for future compatibility TNB 4 0 0 Transmit Number of Buffers Holds the number of buffers in the TDM transmit local buffer Notes 1 The number of transmit buffers equals TNB 1 2 If TDMxTFP TUBM 1 the TNB value is determined by the value of TDMxTFP TCDBL 0x00 1 buffer 0x01 2 buffers ...

Page 1006: ...t the TDM has not received enough bandwidth on the internal MBus and therefore cannot write the data into the destination memory data buffer For details see Section 19 2 6 0 No overrun event has occurred in the TDM local memory 1 An overrun event has occurred in the TDM local memory RFTE 1 0 Receive First Threshold Event This field is set when the first thresholds of all the received data buffers ...

Page 1007: ...the TDM has not received enough bandwidth on the internal MBus and therefore cannot read the data from the data buffers to the TDM local memory For details see Section 19 2 6 0 No underrun event has occurred in the TDM local memory 1 An underrun event has occurred in the TDM local memory TFTE 1 0 Transmit First Threshold Event Indicates whether a first threshold event has occurred TFTE is set when...

Page 1008: ...alue that the SC3400 core should read TDMxRSR TDMx Receive Status Register Offset 0x3F28 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSSS RENS Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 19 43 TDMxRSR Bit Descriptions Name Reset Description Settings 31 3 0 Reserved Write to zero for future compati...

Page 1009: ...d Write to zero for future compatibility TSSS 2 1 0 Transmit Sync Synchronization Status Indicates the transmit sync synchronization status When the synchronization state is SYNC the serial part is synchronized on the transmit sync and new transit data is driven out For details see Section 19 2 4 3 00 HUNT state 01 WAIT state 11 PRESYNC state 10 SYNC state TENS 0 0 Transmit Enable Status Indicates...

Page 1010: ...r occurred The bit is cleared by writing a 1 to it Writing a zero has no effect The parity error is calculated in row resolution 2 channel parameters Thus even when accessing a channel parameter with no parity error this bit indicates a parity error if the other channel has a parity error Moreover the parity error is indicated even if a channel is non active 0 No parity error occurred 1 Parity err...

Page 1011: ...nnects to each SC3400 core so that each SC3400 core can service UART interrupts For details on UART interrupt signal connectivity refer to Chapter 17 Interrupt Processing When accepting an interrupt request an SC3400 core or external host should read the UART status register SCISR to identify the interrupt source and service it accordingly During reception the UART generates an interrupt request w...

Page 1012: ...the full duplex communication to guarantee that no more than one target UART transmits to the URXD signal of the initiator at a given time Receiver wake up can obtain such a protocol see Section 21 2 7 Receiver Wake Up The UART UTXD signal can be configured with full CMOS drive or with open drain drive see Chapter 22 GPIO In both cases the external pull up resistor is needed to avoid floating inpu...

Page 1013: ...3 Figure 20 3 Full Duplex Multiple UART System UART Rx Chip ID n1 UART Tx UTXD URXD UART Rx Chip ID n3 UART Tx UTXD URXD UART Rx Chip ID n2 UART Tx UTXD URXD Initiator Device URXD TxD Note The RC value on the MultiPoint TxD may limit system baud rate R MSC8144E ...

Page 1014: ...ured with open drain drive see Chapter 22 GPIO and an external pull up resistor For details on single wire see Section 21 4 2 Single Wire Operation Figure 20 4 Single Wire Connection UART Rx Chip ID n1 UART Tx TxD UART Rx Chip ID n3 UART Tx TxD UART Rx Chip ID n2 UART Tx TxD Note The RC value on the MultiPoint UTXD might limit system baud rate R Initiator device RXD MSC8144E ...

Page 1015: ...ta bits has a total of 11 bits including a start bit and a stop bit Figure 20 5 UART Data Formats Table 20 1 Examples of 8 Bit Data Format Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Note The address bit identifies the frame as an address character The address bit is bit 7 M 0 or bit 8 M 1 See Section 21 2 7 Receiver Wake Up Table 20 2 Example of 9 Bit Data ...

Page 1016: ...pling for details on adjusting to the received baud rate at the receiver Table 20 3 lists some examples of achieving target baud rates with a CLASS64 clock frequency of 100 MHz using the following formula 20 1 Transmitter The UART transmitter accommodates either 8 bit or 9 bit data characters The state of the M bit in the SCI Control Register SCICR determines the length of the data characters When...

Page 1017: ...er shift register If the Transmit Interrupt Enable TIE bit in the SCICR is set the TDRE flag asserts a UART interrupt request The transmit interrupt service routine responds to this flag by writing another character to the transmitter buffer SCIDR while the shift register is still shifting out the first character If the TDRE flag is set and no new data or break character transferred to the shift r...

Page 1018: ... is in 9 bit data format Reading TDRE bit in the SCISR and then writing new data to T 7 0 in the SCIDR clears the TDRE flag Otherwise the last data transmitted and then UTXD goes to idle condition that is a logic 1 high 3 Repeat step 2 for each subsequent transmission Note The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDR which occurs 9 16ths of...

Page 1019: ... message to the SCIDR 2 Wait for the TDRE flag to go high indicating the transfer of the last frame to the transmit shift register 3 Insert a preamble by clearing and then setting the SCICR TE bit 4 Write the first character of the second message to the SCIDR Another way to separate messages with idle line is to wait until the TC flag is set after writing the last character of the first message to...

Page 1020: ...ously written to the SCI data register Toggle the SCICR TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next character to the SCI data register See Figure 20 7 Queuing an Idle Character 20 1 4 Parity Bit Generation The UART can be configured to enable parity bit generation by the parity enable bit SCICR PE The parity type bit SCICR PT determines whe...

Page 1021: ...enerator is disabled when the baud rate is zero Writing to 5 MSB bits of SCIBR SBR 12 8 has no effect without also writing to 7 LSB of SCIBR SBR 7 0 g Configure GPIO20 for UART URXD see Chapter 22 GPIO Select the UART URXD signal as the external connection via the GPIO port 20 configuration registers Clear the direction bit for GPIO20 in the direction register to select input h Write to the SCICR ...

Page 1022: ...ns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 To locate the start bit data sampling logic searches for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock logic begins to count to 16 Figure 20 8 UART Receiver Block Diagram All Ones M WAKE ILT PE PT RE H 8 7 6 5 4 3 2 1 0 L 11 Bit Receive Shift Reg...

Page 1023: ...sample logic takes samples at RT8 RT9 and RT10 The data bit value is determined by the majority of the samples The noise flag NF is set if not all samples have the same logical value Table 20 5 summarizes the results of the data bit samples Figure 20 9 Receiver Data Sampling Table 20 4 Start Bit Verification RT3 RT5 and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 01...

Page 1024: ...aming error flag FE is set Table 20 6 summarizes the results of the stop bit samples In Figure 20 10 the start bit verification samples RT3 and RT5 determine that the first logic 0 detected is noise and not the beginning of a start bit The RT counter is reset and the start bit search resumes The noise flag is not set because the noise occurred before the start bit was found Table 20 6 Stop Bit Rec...

Page 1025: ...gins again Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 of the next bit are within the bit time and data recovery is successful For this case the noise and framing error flags are not set Figure 20 11 Start Bit Search Example 2 Figure 20 12 Start Bit Search Example 3 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT11 RT10 RT9 RT14 RT13 RT12 RT2 RT1 RT16 RT1...

Page 1026: ...auses the start bit not to be found and resets the RT counter The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge Depending on the timing of the start bit search and on the data the frame may be missed entirely or it may set the framing error flag Figure 20 13 Start Bit Search Example 4 Figure 20 14 Start Bit Search Example 5 Reset RT Co...

Page 1027: ...racter has no stop bit The FE flag is set at the same time that the RDRF flag is set FE inhibits further data reception until it is cleared Clear SCISR FE by reading SCISR and then reading the SCIDR Figure 20 15 Start Bit Search Example 6 Figure 20 16 Start Bit Search Example 7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 Start Bit...

Page 1028: ...t set the RDRF flag again before another break character can set it again 3 The SCIDR is cleared 4 The overrun flag OR noise flag NF parity error flag PF or the receiver active flag RAF is set see the discussion in Section 20 6 20 2 6 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of th...

Page 1029: ...ting device is 9 bit 16 RT cycles 3 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit data character with no errors is 154 147 154 100 4 54 For a 9 bit data character data sampling of the stop bit takes the receiver 10 bit 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character the receiver counts 170 RT cycles...

Page 1030: ...176 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 170 176 170 100 3 53 20 2 7 Receiver Wake Up The receiver can be put into a standby state so that the UART SCI can ignore transmissions intended only for other receivers in multiple receiver systems This is sometimes called putting the receiver to sleep Sett...

Page 1031: ...AKE bit clear setting the SCICR RWU bit after URXD has been idle can cause the receiver to wake up immediately 20 2 7 2 Address Mark Wake Up WAKE 1 In address mark wake up a logic 1 in the MSB position of a frame clears the SCICR RWU bit and wakes up the SCI This frame is considered to contain an address character Hence all data characters should have their MSB at zero Each receiver software evalu...

Page 1032: ...ngle wire operation by setting the SCICR LOOPS bit and the receiver source bit SCICR RSRC Setting the SCICR LOOPS bit disables the path from URXD to the receiver Setting the SCICR RSRC bit connects the receiver input to the output of UTXD Both the transmitter and receiver must be enabled SCICR TE 1 and SCICR RE 1 You can configure UTXD see Chapter 22 GPIO for full CMOS drive or for open drain driv...

Page 1033: ...on Clearing the SCICR RSRC bit connects the transmitter output to the receiver input Both the transmitter and receiver must be enabled SCICR TE 1 and SCICR RE 1 for loop operation 20 4 4 Stop Mode The UART stops its clock to provide reduced power consumption when the GCR1 UART_STC bit is set see Section 8 2 1 General Configuration Register 1 GCR1 on page 8 2 When the UART enters Stop mode the stat...

Page 1034: ...e This section describes the UART SCI module registers which are listed as follows SCI Baud Rate Register SCIBR on page 20 25 SCI Control Register SCICR on page 20 26 SCI Status Register SCISR on page 20 29 SCI Data Register SCIDR on page 20 31 SCI Data Direction Register SCIDDR on page 20 32 Note The UART register use a base address of 0xFFF7F000 Table 20 7 UART Interrupt Sources Source Transmitt...

Page 1035: ... or the SCICR RE bit is set for the first time after reset The baud rate generator is disabled when BR 0 SCIBR SCI Baud Rate Register Offset 0x00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SBR12SBR11SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ...

Page 1036: ...tput is controlled by SCIDDR DDRTX bit If the data direction bit SCIDDR DDRTX for UTXD is set and LOOPS 1 the transmitter output drives UTXD If the data direction bit is clear and LOOPS 1 the SCI transmitter does not drive UTXD 1 Loop operation enabled 0 Normal operation enabled 14 0 Reserved Write to zero for future compatibility RSRC 13 0 Receiver Source Bit When LOOPS 1 determines the internal ...

Page 1037: ...e parity bit 1 Odd parity 0 Even parity TIE 7 0 Transmitter Interrupt Enable Enables the transmit data register empty flag TDRE to generate interrupt requests Note Since SCISR TDRE reset value is 1 setting TIE immediately after reset results in a UART interrupt request regardless of SCICR TE 1 TDRE interrupt source enabled 0 TDRE interrupt source disabled TCIE 6 0 Transmission Complete Interrupt E...

Page 1038: ...k characters 0 No break characters Table 20 10 Loop Functions LOOPS RSRC SCIDDR DDRTX Function 0 x x Normal operation 1 0 0 Loop mode UTXD is not driven by the SCI transmitter 1 0 1 Loop mode UTXD is driven by the SCI transmitter 1 1 0 Single wire mode UTXD acting as an input for the received data The external connection that URXD shares can be configured as a GPIO 1 1 1 Single wire mode with UTXD...

Page 1039: ...r transferred to transmit shift register TC 14 1 Transmit Complete Flag Set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set UTXD becomes idle logic 1 This flag can generate an interrupt request refer to Section 20 5 Clear TC by reading TC...

Page 1040: ...n interrupt request refer to Section 20 5 Clear OR by reading OR then reading R 7 0 in the SCIDR 1 Overrun 0 No overrun NF 10 0 Noise Flag Set when the SCI detects noise on the receiver input NF is set during the same cycle as the RDRF flag but is not set for an overrun Clear NF by reading NF and then reading R 7 0 in the SCIDR 1 Noise 0 No noise FE 9 0 Framing Error Flag Set when a logic 0 is acc...

Page 1041: ... compatibility R8 15 0 Received Bit 8 The ninth data bit received when the SCI is configured for 9 bit data format M 1 T8 14 0 Transmit Bit 8 The ninth data bit transmitted when the SCI is configured for 9 bit data format M 1 13 8 0 Reserved Write to zero for future compatibility 7 0 R 7 0 0 Received Bits 7 0 Received bits seven through zero for 9 bit or 8 bit data formats T 7 0 Transmit Bits 7 0 ...

Page 1042: ... DDRTX Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 13 SCIDDR Bit Descriptions Name Reset Description Settings 31 10 0 Reserved Write to zero for future compatibility DDRTX 9 0 Data Direction Bit TX Controls the TX signal direction in single wire mode refer to Section 20 4 2 1 If TE 1 TX is driven by the transmitter Otherwise if TE 0 UTXD is driven by logic 0 0 UTXD is not driven when t...

Page 1043: ... the cores within MSC8144E as well as by an external host For details see Section 21 3 21 1 Device Level Timers There are four identical quad timer modules in the MSC8144E device Each quad timer module contains four identical timer groups that serve as frequency dividers clock generators and event counters Each 16 bit timer group contains a prescaler a counter a load register a hold register a cap...

Page 1044: ...l invert It selects and optionally inverts a clock source for the primary clock The primary clock can be selected from any of the following Normal clocking CLASS64 clock CLASS64 clock divided by the prescaler 1 2 4 128 Clocking from external events through a timer input signal Clocking in Cascaded mode using an output from another timer in the same quad timer module 3 0 TIMER0 1 TIMER4 2 CLKIN 3 T...

Page 1045: ...mers for its primary clock All timers in the cascade follow the counting mode of the first timer in the chain In Cascade mode a special high speed signal path is used bypassing the timer output flag logic to ensure that the cascaded channels operate as a single synchronous counter You can connect timers using the other non cascade timer modes and selecting the outputs of other timers as a clock so...

Page 1046: ...ich timers can be cascaded The timer with the lowest number must always be the first in the cascade the timer with the second lowest number must be second and so on The timer with the highest number must always be last in the cascade Table 21 2 summarizes the cascading restrictions Table 21 2 Restrictions On Cascading Timers Timer Number Valid Cascade Inputs Legal Values for Cascading using TMRxCT...

Page 1047: ...ogrammed value using the compare functionality and then immediately reinitialize or to count through the compare value until the count rolls over to zero The counting modes define the different modes for clocking the timers The count mode is selected in the TMRxCTL CM field page 21 17 If a timer is programmed to count to a specific value and then stop the TMRCTL CM bit is cleared when the count te...

Page 1048: ...Signed Count 101 Counts the primary clock source while a secondary input provides the count direction up or down for each recognized count Clock to count Count direction Triggered Count 110 Counts the primary clock source only after a rising edge is detected on the secondary input falling edge if TxSCTL IPS is set The counting continues until a compare event occurs or another positive input transi...

Page 1049: ...mer outputs a stream of pulses with the same frequency as the selected clock source cannot be the CLASS64 clock 1 if the timer is set up as follows TMRxCTL CM 001 to count the rising edges of the primary source see Table 21 5TMR 0 3 SCTL 0 3 Bit Descriptions on page 21 19 The Output Flag Mode TMRxCTL OFLM 111 to enable gated clock output while the timer is active The Count Once bit TMRxCTL ONCE 1 ...

Page 1050: ...ially useful for this mode because they give you time to calculate values for the next PWM cycle during the PWM current cycle To set up the timer to run in Variable Frequency PWM mode with compare preload use the set up described here for the desired timer During set up update the TMRxCTL register last because the timer starts counting if the count mode changes to any value other than 000 Set up t...

Page 1051: ...ssful comparison of the timer and the TMRxCMP2 register occurs Compare Load Control 1 CL1 10 to load the compare register when TCF2 is set Compare Load Control 2 CL2 01 to load the compare register when TCF1 is set To service the TCF2 interrupts generated by the Timer the interrupt controller must be configured to enable the interrupts for the timer being used Additionally you must write an interr...

Page 1052: ...TL OFLM 100 the timer is programmed to count upwards It counts until the TMRxCMP1 value is reached reinitializes then counts until the TMRxCMP2 value is reached reinitializes then counts until the TMRxCMP1 value is reached and so on In this Variable Frequency PWM mode the TMRxCMP2 value defines the desired pulse width of the on time and the TMRxCMP1 register defines the off time The Variable Frequ...

Page 1053: ...e width for the logic low part of the timer output and TMRxCMP2 determines the pulse width for the logic high part of the timer output The period of the waveform is determined by the TMRxCMP1 and TMRxCMP2 values and the frequency of the primary clock source See Figure 21 4 Figure 21 4 Variable PWM Waveform To update the duty cycle or period of the waveform update the TMRxCMP1 and TMRxCMP2 values u...

Page 1054: ... changed Each timer in a quad timer module can be programmed for interrupts The available types of interrupts are as follows Timer compare Timer compare 1 Timer compare 2 Timer overflow Timer input edge Each of these different types is ORed together within each timer to generate a single interrupt request signal to the interrupt controller 21 1 6 1 Timer Compare Interrupts Interrupt requests are g...

Page 1055: ...CTL IEF bit 21 2 SC3400 DSP Core Subsystem Timers For a detailed description of the core subsystem timers see the MSC8144 DSP Core Subsystem Reference Manual 21 3 Software Watchdog Timers Since the MSC8144E device contains four cores there are total of five software watchdog timers WDTs one per core and one for an external host However you can allocate the WDTs in any manner to meet your system re...

Page 1056: ...ut period Provide 21 47 s maximum software time out delay for 200 MHz input clock 21 3 2 Modes of Operation The WDT unit can operate in the following modes WDT enable disable mode If the software watchdog timer is not needed user can disable it SWCRR SWEN bit enables the watchdog timer It should be cleared by software after a system reset to disable the software watchdog timer When the watchdog ti...

Page 1057: ...ftware watchdog timer service sequence consists of the following two steps Write 0x556C to the System Watchdog Service Register SWSRR Write 0xAA39 to SWSRR The service sequence reloads the watchdog timer and the timing process begins again If a value other than 0x556C or 0xAA39 is written to the SWSRR the entire sequence must start over Although the writes must occur in the correct order before a ...

Page 1058: ...Watchdog Service Register SWSRR starting the process over When a new value is loaded into SWTC the software watchdog timer is not updated until the servicing sequence is written to the SWSRR If SWCRR SWEN is loaded with 0 the modulus counter does not count 21 4 Timers Programming Model Because they are programmed differently the device level SC3400 DSP core platform level and software watchdog tim...

Page 1059: ...rs Offset 0x18 x 0x40 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CM PCS SC ONCE LEN DIR EIN OFLM Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 21 4 TMR 0 3 CTL 0 3 Bit Descriptions Name Reset Description Settings CM 15 13 0 Count Mode Control the basic counting behavior of the counter Rising edges are counted only when TxSCTL IPS 0 Falling edges are counted only when TxSCTL IPS 1 When count ...

Page 1060: ...d the input Edge Flag in the Timer Channel Status and Control register The Timer n input signals are inputs of the timers in the quad timer module 00 Timer 0 input signal 01 Timer 1 input signal 10 Timer 2 input signal 11 Timer 3 input signal ONCE 6 0 Count Once Selects continuous or one shot counting If counting up a successful compare occurs when the timer reaches TMRxCMP1 value If counting down...

Page 1061: ...cessful compare 011 Toggle the timer output flag when a successful compare occurs 100 Toggle the timer output flag using alternating compare registers 101 Set on compare cleared on secondary input signal s edge 110 Set on compare cleared on timer rollover 111 Enable gated clock output while the timer is active TMR 0 3 SCTL 0 3 Timer Channel Status and Control Register Offset 0x1C x 0x40 Bit 15 14 ...

Page 1062: ...de Specifies the operation of the capture register as well as the operation of the input edge flag 00 Capture function is disabled 01 Load capture register on the rising edge of the secondary count source input 10 Load capture register on the falling edge of the secondary count source input 11 Load capture register on any edge of the secondary count source input MSTR 5 0 Initiator Mode Enables the...

Page 1063: ...ting this bit while the timer is enabled may yield unpredictable results 0 No action 1 Forces the current value of the VAL bit to be written to timer output OPS 1 0 Output Polarity Select Determines the polarity of the output signal 0 True polarity 1 Inverted polarity OEN 0 0 Output Enable Enables the timer output The OPS bit determines the polarity of the output 0 Timer output not enabled 1 Timer...

Page 1064: ...11 10 9 8 7 6 5 4 3 2 1 0 CLV1 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR 0 3 CMPLD2 0 3 Timer Channel Compare Load 2 Registers Offset 0x24 x 0x40 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLV2 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR 0 3 COMSC 0 3 Timer Channel Comparator Status and Offset 0x28 x 0x40 Control Registers Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCF2EN TCF1EN TCF2...

Page 1065: ...he timer and the TMRxCMP1 This bit is sticky and remains set until it is explicitly cleared by writing a zero to this bit location 0 Normal operation 1 Successful compare 1 CL2 3 2 0 Compare Load Control 2 Control when TMRxCMP2 is preloaded with the value from TMRxCMPLD2 00 Never preload 01 Load upon successful compare with the value in TMRxCMP1 10 Load upon successful compare with the value in TM...

Page 1066: ...rs For a detailed information about programming the core subsystem timers see the MSC8144 DSP Core Subsystem Reference Manual TMR 0 3 LOAD 0 3 Timer Channel Load Registers Offset 0x0C x 0x40 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LDV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR 0 3 HOLD 0 3 Timer Channel Hold Registers Offset 0x10 x 0x40 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDV Type ...

Page 1067: ...s SWCRR 0 4 System Watchdog Control Register 0 4 Offset 0x04 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SWTC Type R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWEN SWRI SWPR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Table 21 7 SWCRR 0 4 Bit Descriptions Name Reset Description Settings SWTC 31 16 0xFFFF Software Watchdog Time Count The SWTC field...

Page 1068: ... a hard reset this is the default value after soft reset SWPR 0 1 Software Watchdog Counter Prescale Controls the divide by 65536 WDT counter prescaler 0 The WDT counter is not prescaled 1 The WDT counter clock is divided by 65536 SWCNR 0 4 System Watchdog Count Register 0 4 Offset 0x08 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12...

Page 1069: ...nstructions can be executed between the two writes Reset initializes the SWSRR WS field to 0x0000 SWSRR can be written at any time but returns all zeros when read Table 21 9 defines the bit fields of SWSRR SWSRR 0 4 System Watchdog Service Register 0 4 Offset 0x0E Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WS Type W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 21 9 SWSRR 0 4 Bit Descriptions Name Re...

Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...

Page 1071: ...ouped to maximize the usefulness of the ports in the greatest number of MSC8144E applications Note To understand the port assignment capability described in this chapter you must first understand the Time Division Multiplexing TDM timers UART I2 C PCI Ethernet and ATM UTOPIA peripherals 22 1 Features Following are the key features of the GPIO ports 32 GPIO ports All ports are bidirectional Most po...

Page 1072: ... Bits Pin PDATx Default Input IN1 Default Input IN2 To DED IN1 To DED IN2 From DED OUT2 PDATx Read 0 1 0 1 PAR Open Drain OD 0 Reg From DED OUT1 PSOR 1 0 1 PDATx Write To from internal bus PAR Synchronizer Notes 1 Force Output may be asserted high by dedicated peripheral 2 direction control only when PODRx Reg PDIR Force Output1 Output Enable OE Data Out D OD D OE Pin x x 0 Z 0 d 1 d 1 0 1 0 1 1 1...

Page 1073: ...l bus PAR Synchronizer Notes 1 Force Output may be asserted high by dedicated peripheral 2 direction control only when PODRx Reg PDIR Force Output1 Output Enable OE Data Out D OD D OE Pin x x 0 Z 0 d 1 d 1 0 1 0 1 1 1 Z PAR 1 and PSOR 1 selects this peripheral and PDIR 0 input It is used for bidirectional operation allowing the peripheral to dynamically control the port direction Force Tri state 2...

Page 1074: ...01 Mode 6 0110 Mode 7 0111 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO PCI GPIO 5 GPIO PCI GPIO 6 GPIO PCI GPIO 7 GPIO PCI GPIO 8 GPIO PCI GPIO 9 GPIO PCI GPIO 10 GPIO PCI GPIO 11 GPIO PCI GPIO 12 GPIO PCI GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 UTOPIA GPIO UTOPIA PCI UTOPIA 18 GPIO PCI GPIO UTOPIA 19 GPIO PCI GPIO UTOPIA 20 GPIO PCI GPIO UTOPIA 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO Ethernet PCI GPIO Eth...

Page 1075: ...g PDIR bit is set Each port is configured as a dedicated on device peripheral port if the corresponding PAR bit is set All PAR and PDIR bits are cleared on total system reset configuring all ports as GPIO inputs Data transfer is done through the Pin Data Register PDAT Data written to the PDAT is stored in an output register If a GPIO is configured as an output the output register data is gated ont...

Page 1076: ... TDM6TDAT TDM6TDAT 0 8 IRQ14 1 TDM6TSYN TDM6TSYN 0 9 1 TDM5RDAT TDM5RDAT 0 10 1 TDM5RSYN TDM5RSYN 0 11 1 TDM5TDAT TDM5TDAT 0 12 1 TDM5TSYN TDM5TSYN 0 13 QE_BRGC0 1 TIMER0 TIMER0 0 14 IRQ8 1 URXD URXD 1 15 IRQ9 1 UTXD UTXD 0 16 IRQ0 1 QE_BRGC1 0 17 1 TIMER1 TIMER1 0 18 1 TIMER2 TIMER2 0 19 1 TIMER3 TIMER3 0 20 1 TIMER4 TIMER4 0 21 IRQ1 1 SPICLK 0 22 IRQ4 1 SPIMOSI 0 23 IRQ5 1 SPIMISO 0 24 IRQ6 1 SP...

Page 1077: ...guration of the outputs When a GPIO port has Ethernet functionality see Table 22 1 PODRx does not influence its driving mode PODR Pin Open Drain Register Offset 0x00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OD31 OD30 OD29 OD28 OD27 OD26 OD25 OD24 OD23 OD22 OD21 OD20 OD19 OD18 OD17 OD16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OD15 OD14 OD1...

Page 1078: ...onto the pin When PDAT is read the GPIO pin itself is read If a GPIO port is configured as an input data written to the PDAT register is still stored in the output register but it is prevented from reaching the actual pin When the PDAT register is read the state of the actual pin is read When a GPIO port has Ethernet functionality see Table 22 1 data written to PDATx is stored in the output regist...

Page 1079: ...rt but you must enable the port using the General Input Enable Register GIER to use it See Section 8 2 9 GPIO Input Enable Register GIER on page 8 11 for details PAR Pin Assignment Register Offset 0x18 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 ...

Page 1080: ...wing sequence PSOR PODR PDIR PAR PSOR Pin Special Options Register Offset 0x20 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SO31 SO30 SO29 SO28 SO27 SO26 SO25 SO24 SO23 SO22 SO21 SO20 SO19 SO18 SO17 SO16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO15 SO14 SO13 SO12 SO11 SO10 SO9 SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0 Type R W Reset 0 0 0 0 0 0 0 0...

Page 1081: ... A write of a non zero value lock code is successful only if the current value of the semaphore is zero free This write is defined as a successful lock operation and the written value is the lock code A write of a non zero value lock code is ignored if the current value of the semaphore is non zero locked This write is defined as a failed lock operation since the coded semaphore is considered lock...

Page 1082: ... 24 23 22 21 20 19 18 17 16 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMPVAL Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 23 1 HSMPRx Bit Descriptions Name Reset Description Settings 31 8 0 Reserved Write to zero for future compatibility SMPVAL 7 0 0 Semaphore Value The eight bit coded semaphore value It holds the current semaphore value A non...

Page 1083: ... connection of additional devices to the bus for expansion and system development The bus includes collision detection and arbitration that prevent data corruption if two or more initiators attempt to control the bus simultaneously In the MSC8144E device the maximum SCL frequency is 400 kHz The I2C standard specification requires pull up resistors on SDA and SCL Figure 24 1 is a block diagram of t...

Page 1084: ...ion The module must be enabled before a START condition from a I2 C initiator is detected START condition This condition denotes the beginning of a new data transfer each data transfer contains several bytes of data and awakens all targets This mode is I2C specific Repeated START condition A START condition that is generated without a STOP condition to terminate the previous transfer This mode is ...

Page 1085: ...eceive data Target mode transmit data receive data receive target address after START or restart condition 24 2 2 Input Synchronization The input synchronization block synchronizes the input SCL and SDA signals to the CLASS64 clock and detects transitions of these signals 24 2 3 Digital Input Filter The SCL and SDA signal inputs are filtered to eliminate noise Three consecutive signal samples are ...

Page 1086: ... SDA line while attempting to drive a 1 tries to generate a START or restart at an inappropriate time or detects an unexpected STOP request on the line Arbitration by the initiator in initiator mode is lost under the following conditions Low detected when high expected transmit Ack bit low detected when high expected receive A START condition is attempted when the bus is busy A START condition is ...

Page 1087: ...ace between the serial data line and the data register both transmitting data to and receiving data from the I2 C In transmit mode a write to I2CCR MTX sets the direction to transmit The contents of the parallel register are loaded into a shift register which are then shifted on the SDA line 24 2 8 Address Compare The address compare block determines whether a target has been properly addressed an...

Page 1088: ...f the protocol are described in the following subsections 24 3 1 START Condition When the I2 C bus is not engaged both SDA and SCL lines are at logic high an initiator can initiate a transfer by sending a START condition As shown in Figure 24 2 a START condition is defined as a high to low transition of SDA while SCL is high This condition denotes the beginning of a new data transfer Each data tra...

Page 1089: ...tself by reading the second byte of the message If the device ID is for another receiver device and the third byte is a write command then software can ignore the third byte during the broadcast If the device ID is for another receiver device and the third byte is a read command software must write 0xFF to I2CDR with I2CCR TXAK 1 so that it does not interfere with the data written from the address...

Page 1090: ...rbitration if it transmits a logic 1 on SDA while another initiator transmits a logic 0 The losing initiators immediately switch to target receive mode and stop driving the SDA line In this case the transition from initiator to target mode does not generate a STOP condition Meanwhile the I2C unit sets the I2CSR MAL status bit to indicate the loss of arbitration and as a target services the transac...

Page 1091: ...s high period pulls the SCL line low again 24 3 7 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer Target devices can hold the SCL low after completion of a 1 byte transfer 9 bits In such cases it halts the bus clock and forces the initiator clock into wait states until the target releases the SCL line 24 3 8 Clock Stretching Targets can use the clock syn...

Page 1092: ... MBB to check whether the serial bus is free I2CSR MBB 0 before switching to initiator mode Select initiator mode set I2CCR MSTA to transmit serial data and select transmit mode set I2CCR MTX for the address cycle Write the target address being called into the data register I2CDR The data written to I2CDR 7 1 comprises the target calling address I2CCR MTX indicates the direction of transfer transm...

Page 1093: ...ransmitter by not acknowledging the last byte of data which is done by setting the transmit acknowledge I2CCR TXAK bit before reading the next to last byte of data At this time the next to last byte of data has already been transferred on the I2C interface so the last byte will not receive the data acknowledge when I2CCR TXAK is set For 1 byte transfers a dummy read should be performed by the inte...

Page 1094: ...iting to I2CDR for target transmits or dummy reading from I2CDR in target receive mode The target drives SCL low between byte transfers SCL is released when the I2CDR is accessed in the required mode 24 4 8 Target Transmitter and Received Acknowledge In the target transmitter routine the received acknowledge bit I2CSR RXAK must be tested before sending the next byte of data The initiator signals a...

Page 1095: ...2 C interrupt service routine Deviation from the flowchart may result in unpredictable I2 C bus behavior However in the target receive mode not shown in the flowchart the interrupt service routine may need to set I2CCR TXAK when the next to last byte is to be accepted It is recommended that a sync instruction follow each I2 C register read or write to guarantee in order instruction execution ...

Page 1096: ...CCR MTX 1 0 Target Xmit I2CSR RXAK 1 0 Write next byte to I2CDR EOI Target Received Read I2CDR and store All done Y N Set I2CCR TXAK Read I2CDR dummy read Y N Last byte Next to last Generate Read I2CDR and store EOI Y N Set Initiator Rcv STOP I2CCR TXAK byte Last byte Y N I2CSR RXAK 1 Write next byte to I2CDR 0 EOI Generate Initiator Xmit STOP B 0 1 A 0 A B I2CSR MAAS B 0 1 Clear I2CCR MTX End of ...

Page 1097: ...he reserved fields should not be assumed even though the reserved fields return zero This note does not apply to the I2 C data register I2CDR Note The I2C registers use a base address of 0xFFF24C00 24 5 1 I2 C Address Register I2CADR I2CADR contains the address to which the I2 C interface responds when addressed as a target This is not the address sent on the bus during the address calling cycle w...

Page 1098: ...The serial bit clock frequency of SCL is equal to the CLASS64 clock divided by the divider The frequency divider value can be changed at any point in a program FDR Divider Decimal FDR Divider Decimal 0x00 0x20 0x01 0x21 0x02 0x22 0x03 0x23 0x04 44 0x24 0x05 52 0x25 0x06 60 0x26 32 0x07 64 0x27 36 0x08 72 0x28 32 0x09 88 0x29 40 0x0A 104 0x2A 48 0x0B 112 0x2B 56 0x0C 128 0x2C 48 0x0D 160 0x2D 64 0x...

Page 1099: ...ondition on the bus 0 Issues a STOP condition and changes mode from initiator to target 1 Issues a START condition and initiator mode is selected MTX 4 0 Transmit Receive Mode Select This bit selects the direction of the initiator and target transfers When configured as a target this bit should be set by software according to I2CSR SRW In initiator mode the bit should be set according to the type ...

Page 1100: ...n in transmit mode or b after a START sequence is recognized by the I2 C controller in target mode 1 Byte transfer is completed MAAS 6 0 Module Address as Target When the value in I2CDR matches the calling address or the calling address matches the broadcast address if broadcast mode is enabled this bit is set The processor is interrupted if I2CCR MIEN is set Next the processor must check the SRW ...

Page 1101: ...or can select target transmit receive mode according to the command of the initiator 0 Target receive initiator writing to target 1 Target transmit initiator reading from target MIF 1 0 Module Interrupt The MIF bit is set when an interrupt is pending causing a processor interrupt request if I2CCR MIEN is set MIF is set when one of the following events occurs One byte of data is transferred set at ...

Page 1102: ...lows the I2C module to receive the next byte of data on the I2 C interface In target mode the same function is available after it is addressed I2CDFSRR Digital Filter Sampling Rate Register Offset 0x14 Bit 7 6 5 4 3 2 1 0 DFSR Type R W Reset 0 0 0 1 0 0 0 0 Table 24 6 I2CDFSRR Bit Descriptions Name Reset Description 7 6 0 Reserved Write to zero for future compatibility DFSR 5 0 010000 Digital Filt...

Page 1103: ...cture Problems associated with testing high density circuit boards led to development of this standard under the sponsorship of the test technology committee of IEEE and the joint test action group JTAG The MSC8144E supports circuit board test strategies based on this standard This section covers aspects of JTAG that are specific to the MSC8144E It includes the items that the standard requires to ...

Page 1104: ...C8144E system connections during operation and transparently shift out the result in the BSR Preload values to outputs prior to circuit board testing Disable the drive to outputs during circuit board testing Access the OCE controller and circuits to control a target system Give entry to Debug mode Query identification information manufacturer part number and version from an MSC8144E based device F...

Page 1105: ...ne TDI A test data input with an internal pull up resistor that is sampled on the rising edge of TCK TDO A data output that can be tri stated and actively driven in the SHIFT IR and SHIFT DR controller states TDO changes on the falling edge of TCK TRST An asynchronous reset that provides initialization of the TAP controller and other logic required by the standard 8 Bit Instruction Register TDO TD...

Page 1106: ...ue adjacent to each arc in Figure 25 2 represents the value of the TMS signal sampled on the rising edge of the TCK signal For a description of the TAP controller states refer to the IEEE Std 1149 1 documentation Figure 25 2 TAP Controller State Machine Test Logic Reset Run Test Idle Select DR_SCAN Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR_SCAN Capture IR Shift IR Exit1 IR...

Page 1107: ...e instructions listed in Table 25 3 All other encoding with the exception of the manufacturer private instructions is reserved for future enhancements and is decoded as BYPASS The parallel output of the Instruction Register is reset to 0xF3 in the test logic reset controller state which is equivalent to the IDCODE instruction During the CAPTURE IR controller state the parallel inputs to the instru...

Page 1108: ... the Boundary Scan Register BSR EXTEST also asserts internal reset for the MSC8144E system logic to force a predictable internal state while external boundary scan operations are performed By using the TAP the register can Scan user defined values into the output buffers Capture values presented to inputs Control the direction of bidirectional signals Control the output drive of tri statable outpu...

Page 1109: ...o force a predictable internal state while external boundary scan operations are performed 0xF3 IDCODE Yes Selects the ID Register This instruction is a public instruction to allow the manufacturer part number and version of a component to be determined through the TAP The ID Register configuration is as follows Bits 31 28 Version Information Bits 27 12 Customer Part Number Bits 11 1 Manufacturer ...

Page 1110: ...instruction should be executed to define which OCE is to be activated Note This instruction is valid only if the core processor is running 0xA1 DEBUG_REQUEST Yes Not included in the IEEE Std 1149 1 This public instruction allows you to generate a debug request signal to the MSC8144E When the DEBUG_REQUEST instruction is decoded TDI and TDO connect to the OCE registers In addition ENABLE_ONCE is ac...

Page 1111: ...res This interface is synchronized with the internal clocks derived from the JTAG TCK clock Each OCE module includes an OCE controller an event counter an event detector unit a synchronizer an event selector and a trace unit Note For details on the OCE module features consult the OCE Architecture Manual The JTAG port performs the following tasks via the JTAG OCE module interface Chooses one or mor...

Page 1112: ...ed The number of bits in this stream that is the number of clocks in this state is equal to the number of selected SC3400 cores in the cascade which is four This state is indicated by the CHOOSE_CLOCK_DR signal For example for the four SC3400 cores on the MSC8144E to activate the fourth core in the cascade which is the closest to TDO and the farthest from TDI the data is 1 0 0 0 first a one then t...

Page 1113: ...tion is shifted in during the SHIFT IR state as are all JTAG instructions 25 1 7 RD_STATUS Command In the OCE the status bits are no longer shifted out when shifting in any JTAG instruction Instead there is a special instruction which will return the status of selected core s Figure 25 6 shows an example of CORE_CMD and RD_STATUS instructions Figure 25 6 CORE_CMD and RD_STATUS Flow Wait for core t...

Page 1114: ... for example the command written into the ECR is Write EDCA0_CTRL then the host must again enter the JTAG into SHIFT DR and shift the required data which is to be written into the EDCA0_CTRL via TDI If the command is read some register then the DR chain must be passed again and the contents of the register are shifted out through the TDO output signal When JTAG shifts data to the OCE module the ls...

Page 1115: ...nt Detection Channel 0 by providing an input to the OCE module in the event detection unit and the event selector to or to generate an OCE event EE0 can be programmed to enter the SC3400 core into Debug mode the default right after the SC3400 core is reset Holding EE0 at logic value 1 during and after the reset puts the SC3400 core into Debug mode before the first dispatch occurs In this mode asse...

Page 1116: ...edge 25 1 11 ESEL_DM and EDCA_CTRL Register Programming The Event Selector Mask Debug Mode ESEL_DM register in the OCE programs the event selectors for the debug events The MSC8144E only supports EE0 and EE1 signals Also there is a requirement to block triggering from EE0 if only some SC3400 cores must enter Debug mode The EDCA control register can be used to enable the use of EE1 as the debug ind...

Page 1117: ...Debug mode the EE0 internal signals of all SC3400 cores are unmasked enabling further debug requests To restart the SC3400 cores a go instruction is scanned into all four SC3400 cores When the scan completes the update launches all four SC3400 cores Note When multiple cores are in Debug mode issuing simultaneous go instructions to such cores does not guarantee that the cores exit Debug mode on the...

Page 1118: ...he access used 25 1 16 General JTAG Mode Restrictions The control afforded by the output enable signals using the bsr and the extest instruction requires a compatible circuit board test environment to avoid device destructive configurations You must avoid situations in which the MSC8144E output drivers are enabled into actively driven networks There are two constraints on the JTAG interface The TC...

Page 1119: ...fferent number Refer to the website listed on the back cover of this manual for the information about the contents of this register for current device revisions 25 1 17 2 Boundary Scan Register BSR The MSC8144E BSR contains bits for most device signals and control signals All MSC8144E bidirectional signals have two registers for boundary scan data and are controlled by an associated control bit in...

Page 1120: ... Output Signal Cell O PIN Figure 25 11 Observe Only Input Signal Cell I OBS 1 1 MUX 1 1 MUX G1 C D C D From Last Cell Clock DR Update DR Shift DR 1 EXTEST or CLAMP Data from To Output Buffer 0 Otherwise Logic System To Next Cell G1 1 1 MUX G1 C D From Last Cell Clock DR Data to System Logic Input Pin Shift DR To Next Cell ...

Page 1121: ...ls that are associated with them The BSDL file on the product website describes the boundary sca serial string The three MSC8144E cell types described in this file are depicted in Figure 25 10 through Figure 25 12 which describe the cell structure for each type Figure 25 12 Output Control Cell IO CTL Figure 25 13 General Arrangement of Bidirectional Signal Cells 1 1 MUX G1 1 1 MUX G1 C D C D From ...

Page 1122: ...he Bypass Register is selected the shift register stage is set to a logic zero on the rising edge of TCK in the CAPTURE DR controller state 25 1 17 5 Identification Register When the Identification Register is selected the shift register stage is set to a logic value equal to IDCODE on the rising edge of TCK in the CAPTURE DR controller state It can then be shifted out in the SHIFT DR controller s...

Page 1123: ...nd DSP core subsystem Debug errors for example a transaction request with an illegal address or peripherals errors Support of reading and writing all MSC8144E registers and memories in debug mode by a host processor 25 2 1 Features Table 25 6 describes MSC8144E device debug and profiling features Table 25 6 MSC8144E Debug and Profiling Features Block Name Numberof Blocks in MSC8144 E Supports Inte...

Page 1124: ...occur Assertion of dedicated input signals normally connected to the debugging agent Execution of the DEBUG or DEBUGEV instructions by the core A DPU event depends on the configuration of the DPU and OCE Initiator or peripheral writes a certain value to the GCR2 control register L1 ICache and DCache Activated only when the DSP core subsystem is in the Debug state and certain values are written to ...

Page 1125: ...e debugging agent Execution of the DEBUG or DEBUGEV instruction by the core An event is detected by the DPU depending on the configuration of the DPU and OCE An initiator or peripheral device writes a certain value to GCR2 control register Note See Section 10 6 Real Time Debug Support on page 10 6 for details The DSP core subsystem exits the Debug state when it receives the proper transaction from...

Page 1126: ...t The initiator and target CLASS profiling units provide the following profiling information for initiator and target L2 ICache buses Data acknowledges of read accesses Acknowledged accesses Cycles of non acknowledged accesses Acknowledged supervisor accesses Acknowledged non supervisor accesses Cycles when priority 0 Cycles when priority 1 Cycles when priority 2 Cycles when priority 3 Priority up...

Page 1127: ... Profiling The DMA controller can enter debug mode only as the result of an external debug request When this occurs the channel logic masks all channel requests generated towards the bus interface and finishes all pipelined requests in the bus interface and M bus In this state a debugging agent external to the MSC8144E can access the DMA controller PRAM through JTAG bus 25 2 7 1 Debug Errors The D...

Page 1128: ...equest with an illegal address Illegal addresses are defined as one of the following two cases 1 An address that does not belong to any of the address space windows of the enabled address decoders 2 An address that falls within any of the address space windows of the enabled error address decoders The general interrupt is the logical OR of all the particular interrupts Thus the general interrupt i...

Page 1129: ...ons 25 2 9 1 Trace Buffer The QUICC Engine module provides chip level testing capability through the trace buffer block TRB The TRB provides means of tracing the code ran by the CP communication processor in real time through storing it non intrusively and reporting several internal CP TRB events The QUICC Engine module RISC has 4 kinds of breakpoints for on chip software debugging Instruction bre...

Page 1130: ...ules Each TDM module supports transmit sync error and receive sync error interrupts Table 25 10 lists the TDM debug interrupts See Chapter 19 TDM Interface for details 25 2 10 2 TDM Loopback Support The TDM modules support loopback test mode in which the receiver receives the same data that is transmitted out See Section 19 5 Loopback Support for details Table 25 10 TDM Debug Interrupts DSP core s...

Page 1131: ...dIO complex event is counted twice in the PM module 25 2 12 PCI Debug The PCI system supports an error interrupt to indicate that an address parity data parity or some other system error was detected If any of these errors occur the interrupt is asserted See Chapter 15 PCI for details 25 2 13 Software Watchdog SWT The watchdog timer WDT option prevents system lockup in cases where the software bec...

Page 1132: ... actually written All registers are 32 bits with 16 bit accesses which enable the use of bit mask operations When a 16 bit access is used on the 32 bit registers the software address offset to the MSB part of the registers is equal to the software address offset of the LSB part 2 The LSB part of the address is as shown in the registers memory map and is not influenced by whether the system is Big ...

Page 1133: ...11 10 9 8 7 6 5 4 3 2 1 0 EIS DETB DECB2 DECB1 DECB0 DECA2 DECA1 DECA0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 13 DP_CR Bit Descriptions Name Reset Description Settings 31 30 0 Reserved Write to zero for future compatibility TIDCM 29 28 0 Task ID Comparator Mask Controls the operation of the task ID comparator deciding which part takes part in the comparison The reference program a...

Page 1134: ...tes Debug A interrupt to the EPIC 11 Generates Debug B interrupt to the EPIC 15 0 Reserved Write to zero for future compatibility EIS 14 0 OCE Interrupt Selector A maskable interrupt generated by the OCE is directed either to interrupt Debug A or Debug B 0 A maskable interrupt generates Debug A 1 A maskable interrupt generates Debug B DETB 13 12 0 Trace Buffer Debug Request Interrupt Enable An eve...

Page 1135: ...C 11 Generates Debug B interrupt to the EPIC DECA1 3 2 0 Counter A1 Debug Request Interrupt Enable An event generated by counter A1 of the DPU causes a debug request to the OCE or an interrupt to the EPIC 00 Does not cause an interrupt 01 reserved 10 Generates Debug A interrupt to the EPIC 11 Generates Debug B interrupt to the EPIC DECA0 1 9 0 Counter A0 Debug Request Interrupt Enable An event gen...

Page 1136: ...led 1 Enabled ENCB1 4 0 Counter B1 Enable Indicates whether the counter is disabled or enabled 0 Disabled 1 Enabled ENCB0 3 0 Counter B0 Enable Indicates whether the counter is disabled or enabled 0 Disabled 1 Enabled ENCA2 2 0 Counter A2 Enable Indicates whether the counter is disabled or enabled 0 Disabled 1 Enabled ENCA1 1 0 Counter A1 Enable Indicates whether the counter is disabled or enabled...

Page 1137: ... Counter B2 event debug request DRCB1 4 0 Debug Interrupt Reason is Counter B1 Event Indicates a counter B1 Event debug request 0 No counter B1 event debug request 1 Counter B1 event debug request DRCB0 3 0 Debug Interrupt Reason is Counter B0 Event Indicates a counter B0 Event debug request 0 No counter B0 event debug request 1 Counter B0 event debug request DRCA2 2 0 Debug Interrupt Reason is Co...

Page 1138: ...t fields DP_RPID DPU PID Detection Reference Value Registers Offset 0x0C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RPID Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 16 DP_RPID Bit Descriptions Name Reset Description Settings 31 8 0 Reserved Write to zero for future compatibility RPID 7 0 0...

Page 1139: ...tions Name Reset Description Settings 31 30 0 Reserved Write to zero for future compatibility TDMP 29 28 0 Triad Disable Mode Privilege Level The event disabling the counters belongs to the task described by these bits If the DEBUGEV instruction disables the counters all the programming options mentioned here can be chosen For EDCA events the privilege level can be filtered inside the EDCA itself ...

Page 1140: ...DCA4 in the OCE 0111 Event generated by EDCA5 in the OCE 1000 1110 reserved 1111 The counter is enabled 15 14 0 Reserved Write to zero for future compatibility CEGP 13 12 0 Counted Event Group Privilege Level The source counted by the counter belongs to the task described by these bits 00 The counter counts events that belong to any task 01 The counter only counts events belonging to user tasks de...

Page 1141: ... Bubble due to data memory holds 00101 Not implemented in the MSC8144 00110 Not implemented in the MSC8144 00111 Hold associated with debug Hold due to VTB writes Hold due to internal freeze not used 01000 Hold due to WRQ or WTB Hold due to WRQ flush or atomic operation Hold due to WRQ hazard Hold due to WRQ or WTB full 01010 Hold due to Dcache system Hold due to cacheable access read write back m...

Page 1142: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDMP TDM TENMP TENM Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CEGP CEG CMODE TCEN Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 20 DP_TBC Bit Descriptions Name Reset Description Settings 31 30 0 Reserved Write to zero for future compatibility TDMP 29 28 0 Triad Disable Mode Privilege Level The even...

Page 1143: ...ling event is the result of a supervisor level task detected under the control of DP_CR TIDCM TENM 19 16 0 Triad Enable Mode The event that enables the counters 0000 The counter is disabled 0001 MARK instruction 0010 Event generated by EDCA0 in the OCE 0011 Event generated by EDCA1 in the OCE 0100 Event generated by EDCA2 in the OCE 0101 Event generated by EDCA3 in the OCE 0110 Event generated by ...

Page 1144: ...1 The three counters are controlled by this register and the individual register settings have no effect DP_CA0C DPU Counter A0 Control Register Offset 0x2C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CDMP CDM CENMP CENM Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CEP CE CMODE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 21 DP_CA0C Bi...

Page 1145: ...ongs to a supervisor level task 11 The enabling event is the result of a supervisor level task detected under the control of DP_CR TIDCM CENM 19 16 0 Counter Enable Mode The event that enables the counter 0000 The counter is disabled 0001 MARK instruction 0010 Event generated by EDCA0 in the OCE 0011 Event generated by EDCA1 in the OCE 0100 Event generated by EDCA2 in the OCE 0101 Event generated ...

Page 1146: ...1 Number of L2 ICache thrashes due to instruction access miss 00110 11111 reserved 3 0 Reserved Write to zero for future compatibility CMODE 2 1 0 Counter Mode Specifies the mode of the counter 00 One shot The counter generates an event when it reaches 0 stops counting and disables itself 01 Trace mode The counter value is saved in a shadow register whenever required by the trace buffer The counte...

Page 1147: ...27 26 25 24 23 22 21 20 19 18 17 16 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 22 DP_CA0V Bit Descriptions Name Reset Description Settings 31 0 Reserved Write to zero for future compatibility CV 30 0 0 Counter Value Stores the value of the counter DP_CA1C DPU Counter A1 Control Register Offs...

Page 1148: ...t generated by EDCA5 in the OCE 1000 1111 reserved 23 22 0 Reserved Write to zero for future compatibility CENMP 21 20 0 Counter Enable Mode Privilege Level The event enabling the counter belongs to the task described by these bits If the MARK instruction enables the counter all the programming options mentioned here can be chosen For EDCA events the privilege level can be filtered inside the EDCA...

Page 1149: ...ycles non debug 00001 Application cycles non wait non stop non debug 00010 Number of events generated by the EDCA1 of the OCE CEP bits can be 00 or 01 00011 Number of rollovers by counter A2 CEP bits must be 00 00100 Number of DCache thrashes due to miss 00101 Number of L2 ICache thrashes due to access miss 00110 11111 reserved 3 0 Reserved Write to zero for future compatibility CMODE 2 1 0 Counte...

Page 1150: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 24 DP_CA1V Bit Descriptions Name Reset Description Settings 31 0 Reserved Write to zero for future compatibility CV 30 0 0 Counter Value Stores the value of the counter DP_CA2C DPU Counter A2 Control...

Page 1151: ... EDCA5 in the OCE 1000 1111 reserved 23 22 0 Reserved Write to zero for future compatibility CENMP 21 20 0 Counter Enable Mode Privilege Level The event enabling the counter belongs to the task described by these bits If the MARK instruction enables the counter all the programming options mentioned here can be chosen For EDCA events the privilege level can be filtered inside the EDCA itself 00 The...

Page 1152: ...10 Number of events generated by the EDCA2 of the OCE CEP bits can be 00 or 01 00011 Number of task switches includes the number of times the service of a task started including the first time CEP bits must be 00 00100 11111 reserved 3 0 Reserved Write to zero for future compatibility CMODE 2 1 0 Counter Mode Specifies the mode of the counter 00 One shot The counter generates an event when it reac...

Page 1153: ... 27 26 25 24 23 22 21 20 19 18 17 16 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 26 DP_CA2V Bit Descriptions Name Reset Description Settings 31 0 Reserved Write to zero for future compatibility CV 30 0 0 Counter Value Stores the value of the counter DP_CB0C DPU Counter B0 Control Register Off...

Page 1154: ...t generated by EDCA5 in the OCE 1000 1111 reserved 23 22 0 Reserved Write to zero for future compatibility CENMP 21 20 0 Counter Enable Mode Privilege Level The event enabling the counter belongs to the task described by these bits If the MARK instruction enables the counter all the programming options mentioned here can be chosen For EDCA events the privilege level can be filtered inside the EDCA...

Page 1155: ...000 Clock cycles non debug 00001 Application cycles non wait non stop non debug 00010 Number of events generated by the EDCA3 of the OCE CEP bits can be 00 or 01 00011 Number of interrupts 00100 Number of ICache thrashes due to miss 00101 Number of L2 ICache thrashes due to instruction access miss 00110 11111 reserved 3 0 Reserved Write to zero for future compatibility CMODE 2 1 0 Counter Mode Spe...

Page 1156: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 28 DP_CB0V Bit Descriptions Name Reset Description Settings 31 0 Reserved Write to zero for future compatibility CV 30 0 0 Counter Value Stores the value of the counter DP_CB1C DPU Counter B1 Control...

Page 1157: ... EDCA5 in the OCE 1000 1111 reserved 23 22 0 Reserved Write to zero for future compatibility CENMP 21 20 0 Counter Enable Mode Privilege Level The event enabling the counter belongs to the task described by these bits If the MARK instruction enables the counter all the programming options mentioned here can be chosen For EDCA events the privilege level can be filtered inside the EDCA itself 00 The...

Page 1158: ... 00000 Clock cycles non debug 00001 Application cycles non wait non stop non debug 00010 Number of events generated by the EDCA4 of the OCE CEP bits can be 00 or 01 00011 Number of rollovers by counter B2 CEP bits must be 00 00100 Number of DCache thrashes due to miss 00101 Number of L2 ICache thrashes due to access miss 00110 11111 reserved 3 0 Reserved Write to zero for future compatibility CMOD...

Page 1159: ... 27 26 25 24 23 22 21 20 19 18 17 16 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 30 DP_CB1V Bit Descriptions Name Reset Description Settings 31 0 Reserved Write to zero for future compatibility CV 30 0 0 Counter Value Stores the value of the counter DP_CB2C DPU Counter B2 Control Register Off...

Page 1160: ...t generated by EDCA5 in the OCE 1000 1111 reserved 23 22 0 Reserved Write to zero for future compatibility CENMP 21 20 0 Counter Enable Mode Privilege Level The event enabling the counter belongs to the task described by these bits If the MARK instruction enables the counter all the programming options mentioned here can be chosen For EDCA events the privilege level can be filtered inside the EDCA...

Page 1161: ...events generated by the EDCA5 of the OCE CEP bits can be 00 or 01 00011 Number of task switches includes the number of times the service of a task started including the first time CEP bits must be 00 00100 11111 reserved 3 0 Reserved Write to zero for future compatibility CMODE 2 1 0 Counter Mode Specifies the mode of the counter 00 One shot The counter generates an event when it reaches 0 stops c...

Page 1162: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CV Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 32 DP_CA 0 2 V and DP_CB 0 2 V Bit Descriptions Name Reset Description Settings 31 0 Reserved Write to zero for future compatibility CV 30 0 0 Counter Value Stores the value of the counter DP_TC DPU Trace Control Register Offset 0x7C Bit 31 30 29 28 27 26 25 24...

Page 1163: ...ite access 00 M2 memory 01 Extension of M2 memory 10 M3 memory or L2 ICache 11 Reserved 22 0 Reserved Write to zero for future compatibility PRIV 21 0 Privilege Mode The privilege attribute of the VTB write access 0 User 1 Supervisor GLOBAL 20 18 0 Global Attribute The global attribute of the VTB write access 000 Cacheable write through 001 Cacheable write back 010 Non cacheable write through 011 ...

Page 1164: ... to lose information serving an interrupt between the checking of the TWBA bit and the disabling should be avoided It can be done by disabling the interrupts before the checking of the TWBA bit and enabling them after the disabling When the TMPDIS bit is set the trace logic disregards further inputs 0 Trace logic enabled 1 Trace logic disabled 11 10 0 Reserved Write to zero for future compatibilit...

Page 1165: ...first and last PC of the tasks together with a task flag and all six counter values or for a jump to a subroutine a jump to an interrupt routine or a return from either the task ID and the values of all six counters 0011 reserved 0100 When the SAMPLE bit in the Trace Buffer Control register is set by software at specified points during the application execution the task ID and all six counters 101...

Page 1166: ...wing guidelines to enable disable the trace buffer Always wait until any current flush operations are completed before disabling a trace operation Poll the DP_SR TWBA bit to determine the flush status To prevent any interrupt servicing that may occur between reading the DP_SR TWBA bit and disabling the trace buffer always disable the interrupts before reading the DP_SR TWBA bit and enable them onl...

Page 1167: ...e Bits 4 0 must be written as zeros and are read as zeros Table 25 35 defines the DP_TEA bit fields Table 25 34 DP_TSA Bit Descriptions Name Reset Description Settings SA 31 5 0 Start Address Specifies the end address of the VTB address range 4 0 0 Reserved Write to zero for future compatibility DP_TEA DPU VTB End Address Register Offset 0x84 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EA ...

Page 1168: ...ligned to the value 32 Burst Size programmed in the DP_TC register For a burst size of 4 VBRs the value of TER can be 32 2 n 1 where n is a positive integer Note Bits 4 0 must be written as zeros and are read as zeros Table 25 38 defines the DP_TER bit fields DP_TER DPU Trace Event Request Register Offset 0x88 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TER Type R W Reset 0 0 0 0 0 0 0 0 0...

Page 1169: ... the user its value must be aligned to the value 32 Burst Size programmed in the DP_TC register Note Before changing the value of the DP_TW register you must generate a flush by setting the DP_TC TMPDIS bit Table 25 38 defines the DP_TW bit fields DP_TW DPU Trace Write Pointer Register Offset 0x8C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WP Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1170: ...monitor 64 specific events in addition to counting 64 reference events Each counter is associated with two local control registers A and B that configure the events counted In addition there is a global control register that can be used to enable disable all the counters at one time The benefits of an internal performance monitor are numerous and include the following Because some systems or softw...

Page 1171: ...counter PMC0 does not contain event selection because PMC0 counts only cycles Local control B registers control the start and stop triggering contain the counters threshold values Local control register PMLCB0 which controls PMC0 does not contain threshold information because PMC0 only counts cycles Performance monitor events are signalled by the functional blocks in the integrated device and are ...

Page 1172: ... an overflow when the msb of a counter changes from 0 to 1 For the interrupt to be signalled the condition enable bit PMLCAn CE and performance monitor interrupt enable bit PMGC PMIE must be set When an interrupt is signalled and the freeze counters on enabled condition or event bit PMGC FCECE is set PMGC FAC is set by hardware and all of the registers are frozen Software can clear the interrupt c...

Page 1173: ...unter to increment each time another counter overflows several counters can be chained together to provide event counts larger than 32 bits Each counter in a chain adds 32 bits to the maximum count The register chaining sequence is not arbitrary and is specified indirectly by selecting the register overflow event to be counted Selecting an event has the effect of selecting a source register becaus...

Page 1174: ...lected the trigger off condition is ignored until the trigger on condition has occurred Furthermore when a trigger off condition occurs the counter state is preserved it is not restarted by subsequent trigger on conditions Triggering is disabled when the counter trigger select bits specify itself as the trigger source Similarly triggering is disabled when the trigger control bits are cleared 25 3 ...

Page 1175: ...n L2 ICache bank 2 C8 0 miss which cause to line thrashing in L2 ICache Hit in L2 ICache bank 1 in supervisor mode Ref 12 Hit in L2 ICache bank 2 in supervisor mode Ref 13 Hold cycles in L2 ICache bank 1 in supervisor mode C4 2 Hold cycles in L2 ICache bank 2 in supervisor mode C5 1 Miss in L2 ICache bank 1 in supervisor mode C3 2 Miss in L2 ICache bank 2 in supervisor mode C4 3 Prefetch hit in L2...

Page 1176: ...the inbound buffer is full to priority 3 measured from when SOP received to buffer release transferred on OCN Event asserted for as many clock cycles as this is true C7 3 Clock cycle occurred in which an OCN tag is unavailable any priority Event asserted for as many clock cycles as this is true C8 3 Clock cycle occurred in which an OCN tag is unavailable priority 0 Event asserted for as many clock...

Page 1177: ... which an OCN tag is unavailable priority 0 Event asserted for as many clock cycles as this is true C2 63 Clock cycle occurred in which an OCN tag is unavailable priority 1 Event asserted for as many clock cycles as this is true C3 62 Clock cycle occurred in which an OCN tag is unavailable priority 2 Event asserted for as many clock cycles as this is true C4 60 Clock cycle occurred in which an OCN...

Page 1178: ...rity Event asserted for as many clock cycles as this is true C7 56 Clock cycle occurred in which a misaligned RapidIO tag is unavailable priority 0 Event asserted for as many clock cycles as this is true C4 11 Clock cycle occurred in which a misaligned RapidIO tag is unavailable priority 1 Event asserted for as many clock cycles as this is true C2 62 Clock cycle occurred in which a misaligned Rapi...

Page 1179: ... measured from when EOP received to EOP transferred on OCN Event asserted for as many clock cycles as this is true C1 11 Non idles transmitted This can be used to determine the RapidIO link utilization This is actually 1 2 of the actual count C8 9 NBOUND buffer utilization When this event is selected each bit corresponds to an inbound buffer being used Each bit will be asserted for as long as the ...

Page 1180: ...ditions in counters three and five Furthermore if PMLCBn TRIGONCNTL is 1 the counter begins counting when PMC3 changes value According to the setting in PMLCBn TRIGOFFCNTL the counter ends counting when PMC5 overflows Also although the register settings for PMC5 is not shown PMLCAn CE for this counter must be cleared so that interrupt signalling is not enabled and the counter does not freeze when ...

Page 1181: ...el The performance monitor system includes the following registers Performance Monitor Global Control Register PMGC see page 25 80 Performance Monitor Local Control Register A0 PMLCA0 see page 25 81 Performance Monitor Local Control Register A 1 8 PMLCA 1 8 see page 25 82 Performance Monitor Local Control Register B0 PMLCB0 see page 25 83 Performance Monitor Local Control Register B 1 8 PMLCB 1 8 ...

Page 1182: ...ion Settings FAC 31 0 Freeze All Counters Enables or freezes all counters This bit is set by hardware when a performance monitor interrupt occurs and the FCECE bit is set 0 PMCs increment if permitted by other control bits 1 PMCs do not increment PMIE 30 0 Performance Monitor Interrupt Enable Enables disables the performance monitor interrupt When enabled the interrupt is asserted when a PMC overf...

Page 1183: ... 0 0 Table 25 43 PMLCA0 Bit Descriptions Name Reset Description Settings FC 31 0 Freeze Counter 0 Enables or freezes PMC0 0 PMC0 increments if permitted by other control bits 1 PMC0 disabled and does not increment 30 27 0 Reserved Write to zero for future compatibility CE 26 0 Condition Enable Controls the counter 0 overflow condition This bit should be cleared when PMC0 is used as a trigger or is...

Page 1184: ...ents if permitted by other control bits 1 PMC0 disabled and does not increment 30 27 0 Reserved Write to zero for future compatibility CE 26 0 Condition Enable Controls the counter 0 overflow condition This bit should be cleared when PMCn is used as a trigger or is selected for chaining Note An overflow condition occurs when PMCn msb is set 0 Overflow cannot occur PMC0 cannot cause interrupts or f...

Page 1185: ... event counting to start When the specified counter s TRIGONCNTL event overflows the current counter begins counting No triggering occurs when TRIGONSEL current counter value 25 24 0 Reserved Write to zero for future compatibility TRIGOFFSEL 23 20 0 Trigger Off Select Specifies the number of the counter that triggers event counting to stop When the specified counter s TRIGONCNTL event overflows th...

Page 1186: ...he specified counter s TRIGONCNTL event overflows the current counter begins counting No triggering occurs when TRIGONSEL current counter value 25 24 0 Reserved Write to zero for future compatibility TRIGOFFSEL 23 20 0 Trigger Off Select Specifies the number of the counter that triggers event counting to stop When the specified counter s TRIGONCNTL event overflows the current counter stops countin...

Page 1187: ... 56 55 54 53 52 51 50 49 48 PMC0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PMC0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMC0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMC0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 47 PMC0 B...

Page 1188: ...l registers Table 25 48 defines the PMC 1 8 bit fields PMC 1 8 Performance Monitor Counter 1 8 Offset 0x18 n 0x10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMCn Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMCn Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 48 PMC 1 8 Bit Descriptions Name Reset Description Settings PMCn 31 0 0 Perform...

Page 1189: ... The SEC includes a controller four data channels and six execution units EUs with a shared random number generator RNG that use a common interface to the controller The EUs perform the specific mathematical manipulations required by protocols used in cryptographic processing 26 1 Architecture Overview Because the SEC can act as a master on the internal system bus it does not impose the core proce...

Page 1190: ...riority scheme Data is fed into the execution units through their registers and input FIFOs The execution units read from their input FIFOs and write processed data to their output FIFOs The channel requests that the controller write data from the output FIFOs and registers back to system memory The channel indicates completion by sending a descriptor via an interrupt to the core processor or by a...

Page 1191: ...ch FIFO of one of the channels Based on the services requested by the descriptor header the channel asks the controller to assign the necessary EUs to that channel If all appropriate EUs are already reserved by other channels the channel stalls and waits to fetch data until an appropriate EU is available If multiple channels simultaneously request the same EU the EU is assigned on a weighted prior...

Page 1192: ...parcels as required Note For details see Section 26 2 1 1 Descriptors on page 26 9 Table 26 1 Example Descriptor Field Name Value Description Header 0x20531E0800000000 Example header for IPsec ESP outbound using DES and MD 5 Length0 Extent0 Pointer0 16 0 32 or 36 bit pointer Number of bytes in authenticate key Unused Pointer to authentication key Length1 Extent1 Pointer1 16 0 32 or 36 bit pointer ...

Page 1193: ...ces required and request use of the appropriate EUs from the controller 2 Wait for the controller to grant access to the required EUs 3 Set the appropriate mode bits in the EU s for the required service 4 Fetch data parcels using pointers from the descriptor buffer and place them in either an EU input FIFO or EU registers as appropriate The term data parcel refers here to any input or output of a ...

Page 1194: ... details on configuring signaling see Section 26 5 5 1 Channel Configuration Registers for Channels 1 4 CCR 1 4 on page 26 89 For detail on the writeback fields see Section 26 2 1 1 2 Descriptor Header on page 26 11 26 1 3 4 Encryption and Hashing Many security protocols involve both encryption and hashing of packet payloads To accomplish this without requiring two passes through the data channels...

Page 1195: ... 11i processing and can work together to perform high level cryptographic tasks The SEC EUs include the following PKEU for computing asymmetric key operations including modular exponentiation and other modular arithmetic functions or ECC point arithmetic DEU for performing block cipher symmetric key cryptography using DES and 3DES AESU for performing the Advanced Encryption Standard algorithm MDEU...

Page 1196: ...les to allow concatenation of specific data blocks in memory Figure 26 3 illustrates various ways that descriptors and link tables specify data parcels The first pointer in the descriptor specifies Parcel A using the simplest method the parcel is specified directly through Pointer0 and Length0 The next pointer uses a chain of link tables to specify Parcel B Since J 1 Pointer1 is used as the addres...

Page 1197: ...he descriptor into the Fetch FIFO of one of the SEC channels The channel uses this pointer to read the descriptor into its descriptor buffer Once it obtains the descriptor the SEC uses its bus mastering capability to obtain inputs and write results thus off loading data movement and encryption operations from the core processor Figure 26 3 Descriptors Link Tables and Data Parcels DESCRIPTOR Header...

Page 1198: ...n the descriptor allows for multi algorithm operations that require fetching of multiple keys as well as fetch and return of contexts Any pointer that is not needed can be given a length of zero and the channel skips over the corresponding operations SEC descriptors include scatter gather capability which means that each pointer in a descriptor can be either a direct pointer to a contiguous parcel...

Page 1199: ...y starting at a location given by a POINTER value and accesses the number of bytes defined by a LENGTH or EXTENT value Subsequent data parcels can be accessed by starting where a previous data parcel ended or by starting at a different POINTER location The LENGTH or EXTENT used with any POINTER may be from the same pointer or from a different pointer in the same descriptor Although the EXTENT fiel...

Page 1200: ...ory segments is continued in another link table In a next entry the N bit is set the SEGPTR field gives the address of the next link table and the SEGLEN field must be 0 A chain of link tables may contain any number of link tables Whether the list of memory segments is in a single link table or split into several link tables the last entry in the last link table is a regular entry with the R retur...

Page 1201: ...ned by using Pointer3 yet again this time with length given by Extent4 Assume that for the current descriptor type the Extent4 data parcel is the last one to be accessed through Pointer3 Then the link table entry that supplies the last memory segment for Extent4 has the R bit set signifying that this is the last entry in the chain of link tables Figure 26 7 Descriptors Link Tables and Data Parcels...

Page 1202: ...mplements a snapshot arbiter for each EU When access requests occur the arbiter records the set of pending requests that is it takes a snapshot and then satisfies those requests as the resource becomes available When all requests in the snapshot are satisfied the arbiter takes another snapshot Within a given snapshot the arbiters can use either a weighted priority based scheme or a round robin sch...

Page 1203: ...er The internal bus is 64 bits wide with the controller block as the sole master All accesses to SEC from the system bus go through the controller The controller also directs transfers over the internal bus For core processor controlled access the core processor uses the external bus to access the controller as a slave and the controller relays the read or write accesses to the proper block over t...

Page 1204: ...ats Within a request type the controller grants bus access via the same snapshot scheme used for granting EUs If for example the controller is doing writes it takes a snapshot of the current write requests satisfies them as the bus becomes available then takes another snapshot of write requests and repeats If there are no more write requests in a snapshot the arbiter switches to handling reads It ...

Page 1205: ...orms a transaction as master the intended slave can terminate the transfer due to an error The SEC transaction requests are posted to the device target queue after which the device takes responsibility for either completing the transaction or signalling an error An error in an SEC initiated transaction is also reported by the SEC via the Channel Interrupt Status Register CISR_n The core processor ...

Page 1206: ...interrupt conditions are present the controller deasserts its interrupt output If any interrupts are still pending in the ISR the interrupt output remains asserted The EU interrupt conditions can be blocked at two different levels There is an Interrupt Mask Register in each EU that can block particular interrupt conditions before they reach the EU ISR In addition interrupt conditions from EUs can ...

Page 1207: ...er see Section 26 5 4 4 EU Assignment Status EUASR on page 26 80 Controller Interrupt Enable Register CIER The CIER allows the user to enable or disable interrupt generation by specific sources After reset all sources are disabled When a source is enabled by setting the corresponding bit in the CIER it can set a bit in the Interrupt Status Register ISR which generates an interrupt to the core proc...

Page 1208: ...izes Mode Registers in the assigned EU Initializes EUs and writes to EU registers such as key size and text data size Transfers data parcels up to 32 Kbytes from system memory into the assigned EU input registers and FIFOs This may involve using link tables to gather input data that has been split into multiple segments stored in various locations in system memory For the RAID XOR descriptor type ...

Page 1209: ...report gather and scatter state machine status For details see Section 26 5 5 2 Channel Pointer Status Registers CPSR 1 4 on page 26 92 Current Descriptor Pointer Register CDPR Contains the address for the currently processing descriptor For details see Section 26 5 5 3 Current Descriptor Pointer Register CDPR on page 26 98 Channel Fetch FIFO FF Each channel contains a Fetch FIFO to store a queue ...

Page 1210: ...t generated Note Even if multiple channel done interrupt events are generated by a channel before the first can be cleared by the core processor the interrupt events are not lost The controller queues channel done interrupts from each channel see Section 26 2 4 Controller Interrupts on page 26 18 26 3 2 2 Channel Error Interrupt The Channel Error Interrupt is generated when an error condition occu...

Page 1211: ...DEU Advanced Encryption Standard Execution Unit AESU implementing the Rinjdael symmetric key cipher Message Digest Execution Unit MDEU ARC Four Execution Unit AFEU Kasumi F8 F9 Execution Unit KEU One private internal Random Number Generator RNG Working together the EUs can perform high level cryptographic tasks such as the IPSec Encapsulating Security Protocol ESP and digital signature The followi...

Page 1212: ...res Section 26 5 Programming Model on page 26 66 provides a detailed description of each register and associated register fields 26 4 1 1 PKEU Mode Register This register pacifies the internal PKEU routine to execute The Mode Register is cleared when the PKEU is reset or reinitialized Setting a reserved mode bit generates a data error If the Mode Register is modified during processing a context er...

Page 1213: ... all routines to operate properly is 97 bits internally 128 bits The maximum size to operate properly is 2048 bits A value in bits larger than 2048 results in a data size error 26 4 1 5 PKEU Reset Control Register This register contains three reset options specific to the PKEU 26 4 1 6 PKEU Status Register This register contains 6 fields that reflect the state of PKEU internal fields The PKEU Stat...

Page 1214: ... uses four 2048 bit memories to receive and store operands for the arithmetic operations the PKEU performs In addition results are stored in one particular parameter memory Data addressing within these memories is big endian that is the most significant byte is stored in the lowest address PKEU Parameter Memory A This 2048 bit memory is used typically as an input parameter memory space For modular...

Page 1215: ...Underscore denotes Montgomery format Data Size contents of the Data Size Register Normally loaded with the number of significant bits in N Key Size contents of the Key Size Register Normally loaded with the number of significant bytes in E Sz N The value in the Data Size Register rounded up to the next multiple of 32 This notation recognizes that Data Size is normally related to N making Sz N the ...

Page 1216: ...um Data Size 2048 26 4 1 11 2 MOD_EXP Prime field Fp Exponential mod N and Deconvert From Montgomery Format 0x02 Input N modulus an odd number If an even number is supplied the EVM even modulus error bit in the PKEU Interrupt Status Register is set by the SEC Data Size the number of significant bits in N A field element in Montgomery format E Exponent Key Size the number of significant bytes in E ...

Page 1217: ... Multiply in Affine Coordinates 0x05 Input N modulus an odd number If an even number is supplied the EVM even modulus error bit in the PKEU Interrupt Status Register is set by the SEC Data Size the number of significant bits in N E scalar multiplier key Key Size the number of significant bytes in E A0 A1 multiplicand an input point in affine coordinates A2 0x1 a bit string representing field eleme...

Page 1218: ... described in F2M_R2MODN 0x0D B2 ignored B3 ignored Output B1 B2 E A0 A1 where denotes elliptic curve scalar point multiplication B1 and B2 are in affine coordinates B0 undefined B3 undefined Requirements minimum modulus size 97 bits maximum modulus size 512 bits Point coordinates A0 A1 and elliptic curve parameters A3 B0 are elements of the polynomial field and therefore have fewer significant bi...

Page 1219: ...imum key size 256 bytes 26 4 1 11 8 EC_F2M_PROJ_PTMULT Polynomial Field Elliptic Curve Scalar Point Multiply in Projective Coordinates 0x08 Input N modulus an odd number If an even number is supplied the EVM even modulus error bit in the PKEU Interrupt Status Register is set by the SEC Data Size the number of significant bits in N E scalar multiplier key Key Size the number of significant bytes in...

Page 1220: ...d in projective coordinates and Montgomery format Output B1 B2 B3 A0 A1 A2 B1 B2 B3 where represents an elliptic curve point addition Outputs B1 B2 and B3 are in projective coordinates and Montgomery format B0 elliptic curve b parameter in Montgomery format Requirements minimum modulus size 97 bits maximum modulus size 512 bits Point coordinates A0 A1 A2 B1 B2 B3 and elliptic curve parameters A3 B...

Page 1221: ... in projective coordinates and Montgomery format A3 elliptic curve a parameter in Montgomery format B0 elliptic curve b parameter in Montgomery format B1 B2 B3 second addend in projective coordinates and Montgomery format Output B1 B2 B3 A0 A1 A2 B1 B2 B3 where represents an elliptic curve point addition Outputs B1 B2 and B3 are in projective coordinates and Montgomery format B0 elliptic curve b p...

Page 1222: ...herefore have fewer significant bits than the modulus N 26 4 1 11 13 F2M_R2 Polynomial Field F2m Compute Montgomery Converter Constant 0x0D Input N modulus For a mathematically meaningful result N should be odd Data Size the number of significant bits in N Output B R2 mod N where R 2Sz N Requirements minimum modulus size 97 bits maximum modulus size 512 bits 26 4 1 11 14 F2M_INV Polynomial Field F...

Page 1223: ...me field and are therefore less than the modulus N 26 4 1 11 17 MOD_SUB Prime Field Fp Modular Subtraction 0x20 Input N modulus Data Size the number of significant bits in N A minuend a field element B subtrahend a field element Output B A B mod N a field element Requirements minimum modulus size 97 bits maximum modulus size 2048 bits A and B are elements of the prime field and are therefore less ...

Page 1224: ... B mod N a field element non Montgomery format Requirements minimum modulus size 97 bits maximum modulus size 2048 bits Inputs A and B are elements of the prime field and are therefore less than the modulus N 26 4 1 11 20 F2M_ADD Polynomial Field F2m Modular Addition 0x50 Input N modulus Data Size the number of significant bits in N A First addend a field element B Second addend a field element Ou...

Page 1225: ...ignificant bits in N A Multiplicand as a field element in Montgomery format B Multiplier as a field element in Montgomery format Output B A x B mod N a field element non Montgomery format Requirements minimum modulus size 97 bits maximum modulus size 512 bits A and B are elements of the polynomial field and therefore have fewer significant bits than the modulus N 26 4 1 11 23 RSA_SSTEP RSA Single ...

Page 1226: ... and associated register fields 26 4 2 1 DEU Mode Register The DEU Mode Register contains 3 bits used to program DEU operation The Mode Register is cleared when the DEU is reset or reinitialized Setting a reserved mode bit generates a data error If the Mode Register is modified during processing a context error is generated 26 4 2 2 DEU Key Size Register The key size value indicates the number of ...

Page 1227: ...is assigned The EU error then appears in the channel pointer Status Register see Section 26 5 5 2 Channel Pointer Status Registers CPSR 1 4 on page 26 92 and generates a channel error interrupt to the controller If the Interrupt Status Register is written from the core processor 1s in the value written are recorded in the Interrupt Status Register if the corresponding bit is unmasked in the Interr...

Page 1228: ...key size 16 bytes To operate in 168 bit Triple DES K1 must be written first followed by the write of K2 then K3 Reading any of these memory locations generates an address error interrupt 26 4 2 11 DEU FIFOs The DEU uses an input FIFO output FIFO pair to hold data before and after the encryption process Normally the channels control all access to these FIFOs For core processor controlled operation ...

Page 1229: ...done signaling by interrupt or writeback is undisturbed To signal the ICV checking result by interrupt unmask the ICE bit in the Interrupt Mask Register and turn off the IWSE and AWSE bits in the Channel Configuration Register If there is no ICV mismatch then the normal done signalling by interrupt or writeback occurs When there is an ICV mismatch there is an error interrupt generated to the core ...

Page 1230: ... when the AESU is reset or reinitialized If you specify a key size other than 16 24 or 32 bytes an illegal key size error is generated If the Key Size Register is modified during processing a context error is generated 26 4 3 3 AESU Data Size Register The AESU Data Size Register stores the number of bits in the final message block Acceptable sizes vary depending on the AES mode selected In ECB and...

Page 1231: ...ster is written from the core processor 1s in the value written are recorded in the Interrupt Status Register if the corresponding bit is unmasked in the Interrupt Mask Register All other bits are cleared This register can also be cleared by setting the AESU Reset Control Register RI bit 26 4 3 7 AESU Interrupt Mask Register The AESU Interrupt Mask Register controls the result of detected errors F...

Page 1232: ...essor to read write the contents of the initialization vector IV IV1 holds the least significant bytes LSBs of the initialization vector bytes 1 8 IV2 holds the most significant bytes MSBs of the initialization vector bytes 9 16 The IV must be written prior to the message data If the IV registers are written during message processing or the CBC mode bit is not set a context error is generated The ...

Page 1233: ...is summarized in Figure 26 8 The context for CCM encryption MAC generation is Reg 1 2 are session specific and hold the 128 bit Initialization Vector from memory Reg 3 4 contains 128 bits of zero padding Reg 5 6 are a session specific counter Initial Counter Value from memory Reg 7 has the Counter Modulus Exponent msb to lsb Should be fixed at 0x0000_0080 Note The counter modulus for CCM mode is c...

Page 1234: ... the full 128 bits The core processor must only append the most significant 64 bits to the frame as the MIC 6 The counter value is incremented and is then encrypted with the symmetric key The result is then hashed with the first block of plaintext to produce the first block of cipher text The ciphertext is placed in the AESU output FIFO 7 The counter continues to be incremented and encrypted with ...

Page 1235: ...e AESU output FIFO while simultaneously in CBC fashion a copy of the first block of plaintext is hashed with the output of encryption of the IEEE Std 802 11 frame header The output is encrypted with the symmetric key 3 As each ciphertext block is converted to plaintext the plaintext is CBC encrypted When the final plaintext block has been processed the CBC MAC MAC Tag is written to Context Registe...

Page 1236: ... dequeues it causes an error interrupt of type AE from the EU Overflows and underflows caused by reading or writing the AESU FIFOs are reflected in the AESU Interrupt Status Register The AESU fetches data 128 bits at a time from the input FIFO During processing the input data is encrypted or decrypted with the key and initialization vector CBC mode only and the results are placed in the output FIF...

Page 1237: ...an error interrupt to the core processor but no done interrupt or writeback The following subsections include general descriptions of the MDEU registers and structures Section 26 5 Programming Model on page 26 66 provides a detailed description of each register and associated register fields 26 4 4 1 MDEU Mode Register The MDEU Mode Register is used to program the function of the MDEU Bits 7 0 of ...

Page 1238: ...MDEU Data Size Register indicates the number of bits of data to be processed The Data Size field is a 21 bit signed number Values written to this register are added to the current register value Multiple writes are allowed The MDEU processes data when there is a positive value in this register and there is data available in the MDEU input FIFO Negative values can occur during inbound processing wh...

Page 1239: ... user The MDEU Status Register is read only Writing to this location result in an address error being reflected in the MDEU Interrupt Status Register 26 4 4 6 MDEU Interrupt Status Register The Interrupt Status Register indicates which unmasked errors have occurred and have generated error interrupts to the channel Each bit in this register can only be set if the corresponding bit of the MDEU Inte...

Page 1240: ...during the write operation the core processor data bus is not read Hence any data value is accepted Normally a write operation with a zero data value is performed Reading from this register is not meaningful but a zero value is always returned and no error is generated Writing to this register is merely a trigger causing the MDEU to process the final block of a message allowing it to initiate a do...

Page 1241: ...ywhere in this address space returns all zeros When the core processor writes to the MDEU FIFO using core processor controlled access it can write to any FIFO address by byte 4 byte or 8 byte accesses The MDEU assembles these bytes from left to right that is the first bytes written are placed in the most significant bit positions Whenever the MDEU accumulates 8 bytes these 8 bytes are automaticall...

Page 1242: ...ge processing is complete and the output data is read the AFEU will make the current context data available for reads via the output FIFO The AFEU context is 259 bytes long Note After the initial key permute to generate a context for an AFEU encrypted session all subsequent messages will re use that context such that it is loaded modified during the encryption and unloaded similar to the use of a ...

Page 1243: ...ata size The message data size must be written separately Note When reloading an existing context using core processor controlled access the user must write the context to the input FIFO then write the context size always 2072 bits The write of the context size indicates to the AFEU that all context has been loaded The user then writes the message data size to the context Data Size Register After ...

Page 1244: ...terrupt Mask Register The Interrupt Mask Register controls the result of detected errors For a given error as defined in Section 26 5 10 6 AFEU Interrupt Status Register AFEUISR on page 26 155 if the corresponding bit in this register is set the error is disabled no error interrupt occurs and the Interrupt Status Register is not updated to reflect the error If the corresponding bit is not set then...

Page 1245: ...r specifies which through the CS bit of the AFEU Mode Register see Section 26 4 5 1 AFEU Mode Register See Section 26 4 5 10 1 AFEU FIFOs for more about addressing the FIFOs 26 4 5 9 2 AFEU Context Memory Pointer Register The context memory pointer register holds the internal context pointers that are updated with each byte of message processed These pointers correspond to the values of I J and Sb...

Page 1246: ...d into the input FIFO when the AFEU End_of_Message Register is written The output FIFO is readable by byte 4 byte or 8 byte accesses When all 8 bytes of the header are read that 8 bytes is automatically dequeued from the FIFO so that the next 8 bytes if any becomes available for reading If any byte is read twice between dequeues it causes an error interrupt of type AE from the EU Overflows and und...

Page 1247: ...U is reset or reinitialized Setting a reserved mode bit generates a data error Setting both the GSM and EDGE bits to one generates a data error If the KEU Mode Register is modified during processing a context error is generated 26 4 6 2 KEU Key Size Register The KEU Key Size Register stores the number of bytes in the key It should be set to 16 bytes This register is cleared when the KEU is reset o...

Page 1248: ...ress error being reflected in the KEU Interrupt Status Register 26 4 6 6 KEU Interrupt Status Register The Interrupt Status Register indicates which unmasked errors have occurred and have generated error interrupts to the channel Each bit in this register can only be set if the corresponding bit of the KEU Interrupt Mask Register is zero see Section 26 5 11 7 KEU Interrupt Mask Register KEUIMR on ...

Page 1249: ...age Register signals the KEU that the final message block is written to the input FIFO Writing to this register causes the KEU to process the final block of a message allowing it to signal a done interrupt When processing the last block the value in the Data Size Register determines how many bits of the final message set 1 64 are processed The value written to this register does not matter A read ...

Page 1250: ...eration a frame is received and processed in its entirety with the KEU performing session specific initialization using the contexts of KEU IV_1 and IV_2 registers The KEU context data and IV_1 registers should only be unloaded reloaded when the processing of a frame is discontinued prior to completion then processing is resumed 26 4 6 14 KEU Key Data Registers_ 1 2 Confidentiality Key The first p...

Page 1251: ... are automatically padded with zeros and forced into the input FIFO when the KEU End_of_Message Register is written The output FIFO is readable in byte 4 byte or 8 byte increments When all 8 bytes of the header are read that 8 bytes is automatically dequeued from the FIFO so that the next 8 bytes if any becomes available for reading If any byte is read twice between dequeues it causes an error int...

Page 1252: ...ble location but all mode bits are currently reserved It is documented for the sake of consistency with the other EUs 26 4 7 2 RNG Data Size Register The RNG Data Size Register is used to tell the RNG to begin generating random data The actual contents of the Data Size Register do not affect the operation of the RNG After a reset and prior to the first write of data size the RNG builds entropy wit...

Page 1253: ...26 183 if the corresponding bit in this register is set then the error is disabled no error interrupt occurs and the Interrupt Status Register is not updated to reflect the error If the corresponding bit is not set then upon detection of an error the Interrupt Status Register is updated to reflect the error causing assertion of the error interrupt signal and causing the module to halt processing 2...

Page 1254: ...26 87 Channels Channel Configuration Registers 1 4 CCR 1 4 page 26 89 Channel Pointer Status Registers 1 4 CPSR 1 4 page 26 92 Channel Current Descriptor Pointer Registers 1 4 CDPR 1 4 page 26 98 Channel Fetch FIFOs 1 4 CFF 1 4 page 26 99 Channel Descriptor Buffers page 26 100 PKEU PKEU Mode Register PKEUMR page 26 101 PKEU Key Size Register PKEUKSR page 26 103 PKEU AB Size Register PKEUABSR page ...

Page 1255: ...ers AESUKR 1 3 page 26 135 AESU Input FIFO Output FIFO page 26 136 MDEU MDEU Mode Register MDEUMR page 26 137 MDEU Key Size Register MDEUKSR page 26 139 MDEU Data Size Register MDEUDSR page 26 139 MDEU Reset Control Register MDEURCR page 26 140 MDEU Status Register MDEUSR page 26 141 MDEU Interrupt Status Register MDEUISR page 26 142 MDEU Interrupt Mask Register MDEUIMR page 26 144 MDEU ICV Size R...

Page 1256: ...Register KEUICVIR page 26 174 KEU IV2 Register KEUIV2R page 26 175 KEU Context Registers 1 6 KEUCR 1 6 page 26 176 KEU Key Data Registers 1 2 KEUKDR 1 2 page 26 177 KEU Key Data Registers 3 4 KEUKDR 3 4 page 26 178 KEU Input FIFO Output FIFO page 26 178 Random Number Generator RNG RNG Mode Register RNGMR page 26 179 RNG Data Size Register RNGDSR page 26 180 RNG Reset Control Register RNGRCR page 2...

Page 1257: ...4 J4 Extent4 Eptr4 Pointer4 Pointer 5 Length5 J5 Extent5 Eptr5 Pointer5 Pointer 6 Length6 J6 Extent6 Eptr6 Pointer6 Table 26 4 Descriptor Types Value1 binary Descriptor Type Notes 0000_02 aesu_ctr_nonsnoop AESU CTR non snooping 0001_02 common_nonsnoop Common non snooping non PKEU non AFEU 0010_03 hmac_snoop_no_afeu Snooping HMAC non AFEU 0011_0 Reserved 0100_0 Reserved 0101_0 common_nonsnoop_afeu ...

Page 1258: ...Descriptor Format Summary Descriptor Type field type Pointer0 Pointer 1 Pointer2 Pointer3 Pointer4 Pointer5 Pointer6 0000_0 aesu_ctr_ nosnoop Length nil Cipher IV Cipher Key In FIFO Out FIFO Cipher IV Out nil Extent undefined undefined undefined nil nil nil undefined 0001_0 common_ nosnoop for DES KEU F8 RNG AES CCM Length nil Cipher IV incl ICV In Cipher Key In FIFO Out FIFO Cipher IV Out incl IC...

Page 1259: ... Extent undefined undefined undefined nil nil nil undefined 0100_1 pkeu_ptmul Length N E Build B1 Out B2 Out B3 Out nil Extent undefined undefined undefined nil nil nil undefined 0101_1 pkeu_ptadd_dbl Length N Build B2 B3 B1 Out B2 Out B3 Out Extent undefined undefined undefined nil nil nil undefined 1000_1 outbound tls_ssl_ block Length MAC Key Cipher IV Cipher Key In FIFO Auth CIpher In FIFO Cip...

Page 1260: ...teback rows and described in Table 26 8 1001_1 inbound tls_ssl_ stream Length MAC Key Cipher IV Cipher Key nil In FIFO Auth CIpher Out FIFO Cipher IV Out Extent undefined undefined undefined In FIFO Auth only MAC In MAC Out undefined 1010_1 raid_xor Length nil nil nil In 1 In 2 In 3 Out Extent undefined undefined undefined nil nil nil undefined others Reserved Bit 63 62 61 60 59 58 57 56 55 54 53 ...

Page 1261: ... the Mode Register in the selected EU 39 35 DESC_TYPE Descriptor Type Along with the DIR field this determines the sequence of actions to be performed by the channel and selected EUs using the blocks of data listed in the rest of the descriptor The determined attributes include the direction of data flow for each data block which EU primary or secondary to access what snooping options to use and w...

Page 1262: ...E When DONE writeback is used then at the completion of descriptor processing this byte is written with the value 0xFF To determine when done writeback is used see the CDWE NT and CDIE fields in the Channel Configuration Register Section 26 5 5 1 Channel Configuration Registers for Channels 1 4 CCR 1 4 on page 26 89 55 29 Reserved 28 27 ICCR0 Integrity Check Comparison Result from Primary These bi...

Page 1263: ...even parcels of input and output data In these cases it is necessary to use one POINTER field to address a sequence of data parcels LENGTH and EXTENT fields normally specify the sizes of data parcels In some cases however the POINTER field is zero and the LENGTH and or EXTENT fields simply specify values to write to an EU The J bit in each pointer is used to enable the scatter gather feature If a ...

Page 1264: ...link table and the SEGLEN field must be 0 A chain of link tables may contain any number of link tables Bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field SEGLEN R N EPTR Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field SEGPTR Table 26 10 Link Table Field Definitions Fields Description Settings SEG...

Page 1265: ...2 PRIOR ITY S W R Type R W Reset 0x00000000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field CHN3_EU_PR_CNT CHN4_EU_PR_CNT CHN3_BUS_PR_CNT CHN4_BUS_PR_CNT R W R W Reset 0x00000000 Table 26 11 Master Control Register Bit Field Descriptions Bits Reset Description Settings 63 42 0 Reserved Write to zero for future compatibility PRIORITY 41 40 0 Priority ...

Page 1266: ...st also be set to zero and the controller assigns EUs on a purely round robin basis If set to non zero CHN3_EU_PR_CTR must also be set to a different non zero value CHN3_BUS_PR_CNT 16 8 0 Channel 3 Bus Priority Counter This counter is used by the controller to determine when Channel 3 has been denied access to the bus long enough to warrant immediate elevation to level 2 priority Note If set to ze...

Page 1267: ...evision Register CIDR Controller Identification Register Offset 0xC1020 Bits 63 0 ID Type R Reset 0x0030000200000000 CIPBRR Controller IP Block Revision Register Offset 0xC1BF8 Bits 63 48 47 40 39 32 31 24 23 16 15 8 7 0 Field IP_ID IP_MJ IP_MN IP_INT IP_CFG Type R Reset 0x0030 0x00 0x02 0x00 0x00 0x00 0x00 Table 26 12 CIPBRR Bit Field Descriptions Bits Reset Description Settings IP_ID 63 48 0x003...

Page 1268: ...rite to zero for future compatibility AFEU 59 56 0x0 AFEU Indicates the AFEU channel assignment See Table 26 14 55 52 0xF Reserved Write to zero for future compatibility MDEU 51 48 0x0 MDEU Indicates the MDEU channel assignment See Table 26 14 47 44 0xF Reserved Write to zero for future compatibility AESU 43 40 0x0 AESU Indicates the AESU channel assignment See Table 26 14 39 36 0xF Reserved Write...

Page 1269: ...ate interrupts to the core processor Table 26 15 describes the register field names in the CIER Table 26 14 Channel Assignment Value Value Channel 0x0 No channel assigned 0x1 Channel 1 0x2 Channel 2 0x3 Channel 3 0x4 Channel 4 0xA 0xE Undefined 0xF Unavailable CIER Controller Interrupt Enable Register Offset 0xC1008 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field ITO Subfield Type R W R...

Page 1270: ...The Channel Status Register must be read to determine the exact cause of the error 0 Error detection interrupt disabled 1 Error detection interrupt enabled CHN3 Dn 36 0 Channel 3 Done Interrupt Indicates whether Channel 3 has completed its operation 0 Done detection interrupt disabled 1 Done detection interrupt enabled CHN2 Err 35 0 Channel 2 Error Interrupt Indicates whether a Channel 2 error occ...

Page 1271: ...ed its operation 0 Done interrupt disabled 1 Done interrupt enabled 15 14 0 Reserved Write to zero for future compatibility AFEU Err 13 0 AFEU Error Interrupt Indicates whether the AFEU generated an error 0 Error interrupt disabled 1 Error interrupt enabled AFEU Dn 12 0 AFEU Done Indicates whether the AFEU has completed its operation 0 Done interrupt disabled 1 Done interrupt enabled 11 10 0 Reser...

Page 1272: ...sabled 1 Error interrupt enabled DEU Dn 0 0 DEU Done Indicates whether the DEU has completed its operation 0 Done interrupt disabled 1 Done interrupt enabled CISR Controller Interrupt Status Register Offset 0xC1010 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field ITO Subfield Type R Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field DONE Overflow CHN_4 CHN_3 CHN_2 CH...

Page 1273: ...ror occurred The Channel Status Register must be read to determine the exact cause of the error 0 No error detected 1 Error detected CHN4 Dn 38 0 Channel 4 Done Interrupt Indicates whether Channel 4 has completed its operation 0 Not done 1 Operation done CHN3 Err 37 0 Channel 3 Error Interrupt Indicates whether a Channel 3 error occurred The Channel Status Register must be read to determine the ex...

Page 1274: ...AFEU Dn 12 0 AFEU Done Indicates whether the AFEU has completed its operation 0 Not done 1 Operation done 11 10 0 Reserved Write to zero for future compatibility MDEU Err 9 0 MDEU Error Interrupt Indicates whether the MDEU generated an error 0 No error detected 1 Error detected MDEU Dn 8 0 MDEU Done Indicates whether the MDEU has completed its operation 0 Not done 1 Operation done 7 6 0 Reserved W...

Page 1275: ... a few cycles after it is cleared using the CICR CICR Controller Interrupt Clear Register Offset 0xC1018 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field ITO Subfield Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field DONE Overflow CHN_4 CHN_3 CHN_2 CHN_1 Subfield CH4 CH3 CH2 CH1 Err Dn Err Dn Err Dn Err Dn Reset 0x0000 R W R W Bits 31 30 29 28 27 26 25 24 2...

Page 1276: ...ears the KEU error status bit 0 No action 1 Clear status bit KEU Dn 24 0 KEU Done Clears the KEU done status bit 0 No action 1 Clear status bit 23 22 0 Reserved Write to zero for future compatibility PKEU Err 21 0 PKEU Error Interrupt Clears the PKEU error status bit 0 No action 1 Clear status bit PKEU Dn 20 0 PKEU Done Clears the PKEU done status bit 0 No action 1 Clear status bit 19 18 0 Reserve...

Page 1277: ...it 3 2 0 Reserved Write to zero for future compatibility DEU Err 1 0 DEU Error Interrupt Clears the DEU error status bit 0 No action 1 Clear status bit DEU Dn 0 0 DEU Done Clears the DEU done status bit 0 No action 1 Clear status bit CCR1 Channel Configuration Registers Offset 0xC1108 CCR2 Offset 0xC1208 CCR3 Offset 0xC1308 CCR4 Offset 0xC1408 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 F...

Page 1278: ... state machine to the idle state 0 No special action 1 Initiates a soft reset of the channel clearing all of its internal state 31 9 0 Reserved Write to zero for future compatibility BS 8 0 Burst Size This bit determines the burst size used by the SEC to access long text data parcels in main memory 0 Burst size is 64 bytes 1 Burst size is 128 bytes IWSE 7 0 ICV Writeback Status Enable If this bit ...

Page 1279: ...done interrupt Depending on the setting of the NT and DN bits the channel sends an interrupt to the core processor at the end of every descriptor processing or at the end of descriptors for which the DN bit in the header is set See Section 26 3 2 Channel Interrupts on page 26 22 for details 0 No action 1 Clear status bit 0 0 Reserved Write to zero for future compatibility Note The done interrupt d...

Page 1280: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 Field MI MO PR SR PG SG PRD SRD PD SD Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field DOF SOF MDTE SGDL ZE FPZE IDH IEUA R EUE GBE GRLE SBE SRLE DWORD_NUM Type R W Reset 0x0000 Table 26 19 CPSR Bit Field Descriptions Bits Reset Description Settings 63 61 0 Reserved Write to zero for future compatibility FF_ COUNTER 60 56 0 Fetch File ...

Page 1281: ...put snooping disabled 1 Data output snooping by secondary EU enabled PR 23 0 Primary EU Assignment Request This bit is set when descriptor processing is initiated by the channel and the Op_0 field in the descriptor header contains a valid EU identifier The bit is cleared when the request is granted which is reflected by the setting of the PG bit 0 Primary EU assignment request is inactive 1 Channe...

Page 1282: ... another write is made to the fetch FIFO When this bit is set the channel stops and activates an error interrupt The channel does not start again until a continue or reset is generated via the CCR You can clear this bit by writing a 1 to this bit 0 No error detected 1 Error detected SOF 14 0 Single Fetch FIFO Write Overflow Error Set when the channel fetch FIFO is full and another write is made to...

Page 1283: ...7 0 Gather Boundary Error Set when the gather pointer straddles both a primary and secondary EU data transfer 0 No error detected 1 Error detected GRLE 6 0 Gather Run Length Error Set when the total data size covered by a gather link table does not match the total data size from the main descriptor 0 No error detected 1 Error detected SBE 5 0 Scatter Boundary Error Set when the scatter pointer str...

Page 1284: ...ANS_INBOUND_DONE Table 26 21 CHN_STATE Field Values Value Channel State 0x00 IDLE 0x01 PROCESS_HEADER 0x02 FETCH_DESCRIPTOR 0x03 CHANNEL_DONE 0x04 CHANNEL_DONE_IRQ 0x05 CHANNEL_DONE_WRITEBACK 0x06 CHANNEL_DONE_NOTIFICATION 0x07 CHANNEL_ERROR 0x08 REQUEST_PRI_CHA 0x09 INC_DATA_PAIR_POINTER 0x0A DELAY_DATA_PAIR_UPDATE 0x0B EVALUATE_DATA_PAIRS 0x0C WRITE_RESET_PRI 0x0D RELEASE_PRI_CHA 0x0E WRITE_RESE...

Page 1285: ...ELEASE_SEC_CHA 0x27 RESET_CHANNEL 0x28 WRITE_DATASIZE_PRI_POST 0x29 RESET_RELEASE_ALL 0x2A RESET_RELEASE_ALL_DELAY 0x2B REQUEST_SEC_CHA 0x2C WRITE_DATASIZE_SEC 0x2D WRITE_ICV_SIZE 0x2E WRITE_SEC_CHA_GO_SNOOPOUT 0x2F WRITE_PRI_CHA_GO_SNOOPIN 0x30 WRITE_SEC_CHA_GO_SNOOPIN 0x31 DELAY_1CYCLE 0x33 TRANS_EXTENT_READ 0x34 TRANS_EXTENT3 0x35 TRANS_EXTENT4 0x36 XOR_WRITE_READ_REG 0x37 DELAY_SEC_DONE_TLS 0x...

Page 1286: ...4 3 2 1 0 Field CUR_DES_PTR_ADRS Type R Reset 0x0000 Table 26 22 CDPR Bit Field Descriptions Bits Reset Description 63 36 0 Reserved Write to zero for future compatibility EPTR 35 32 0 Extended Pointer Concatenated as the upper 4 bits of the pointer address when extended mode is selected EAE is high see Table 26 18 for details CUR_DES_PTR_ADRS 31 0 0 Current Descriptor Pointer Address Pointer to t...

Page 1287: ...the Extended Fetch Address must be written before or concurrent with the Fetch Address Specifying a FETCH_ADRS of 0 causes the channel to generate an error and stop The bits in the CFF perform the functions described in Table 26 22 CFF1 Channel Fetch FIFOs Offset 0xC1148 CFF2 Offset 0xC1248 CFF3 Offset 0xC1348 CFF4 Offset 0xC1448 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type W Re...

Page 1288: ...tor see Section 26 2 1 1 1 Descriptor Structure on page 26 10 Note The DBs are located at the following locations Channel 1 Offsets 0xC1180 0xC11BF Channel 2 Offsets 0xC1280 0xC12BF Channel 3 Offsets 0xC1380 0xC13BF Channel 4 Offsets 0xC1480 0xC14BF 0 15 16 17 23 24 27 28 31 32 63 DB0 Header Reserved DB1 Length0 J0 Extent0 Eptr0 Pointer0 DB2 Length1 J1 Extent1 Eptr1 Pointer1 DB3 Length2 J2 Extent2...

Page 1289: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field ROUTINE Type R W Reset 0x0000 Table 26 24 PKEUMR Field Descriptions Name Reset Description Settings 63 8 0 Reserved Write to zero for future compatibility ROUTINE 7 0 0 Routine Specifies the PKEU routine to run See Table 26 29 for values See Section 26 4 1 11 PKEU Routines on...

Page 1290: ...point in projective coordinates 0x0D F2M_R2 F2m Compute Montgomery converter R2 mod N 0x0E F2M_INV F2m Invert mod N 0x0F MOD_INV FP Invert mod N 0x10 MOD_ADD FP Add mod N 0x20 MOD_SUB FP Subtract mod N 0x30 MOD_MULT1_MONT FP Multiply mod N in Montgomery format 0x40 MOD_MULT2_DECONV FP Multiply mod N and deconvert from Montgomery format 0x50 F2M_ADD F2m Add mod N 0x60 F2M_MULT1_MONT F2m Multiply mo...

Page 1291: ...pt Status Register PKEUKSR PKEU Key Size Register Offset 0xCC008 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Key Size Type R W Reset 0x0000 Table 26 26 ...

Page 1292: ...ssing an error is generated An illegal data size error will be generated as follows All non ECC routines with a data size 256 generate an illegal data size error All ECC routines with a data size 64 generate an illegal data size error An AB Size 0 either intentionally written or by ignoring and not writing at all generates an illegal size error except for routines that do not require an A or B ope...

Page 1293: ...for information only The minimum size valid for all routines to operate properly is 97 bits internally 128 bits The maximum size to operate properly is 2048 bits A value in bits larger than 2048 result in a data size error PKEUDSR PKEU Data Size Register Offset 0xCC010 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33...

Page 1294: ...EU interrupts signalling done and error to reset It further resets the state of the PKEU Interrupt Status Register 0 No reset 1 Reset interrupt logic MI 1 0 Module Initialization Setting this reinitializes the PKEU to accept another request without forcing the Interrupt Mask Register to change This module initialization includes execution of an initialization routine completion of which is indicat...

Page 1295: ...ettings 63 7 0 Reserved Write to zero for future compatibility Z 6 0 Zero This bit reflects the state of the PKEU zero detect bit when last sampled Only specific instructions within routines cause the Z bit to be modified Therefore use the value of this bit carefully 0 Zero not detected 1 Zero detected HALT 5 0 Halt Indicates whether the PKEU is halted due to an error Note Because the error causin...

Page 1296: ... and generates a channel error interrupt to the controller DI 1 0 Done Interrupt This status bit reflects the state of the done interrupt signal as sampled by the controller Interrupt Status Register see Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 PKEU is not signalling done 1 PKEU is signalling done RD 0 0 Reset Done This status bit when high indicates that the PKEU...

Page 1297: ...rror was detected while the PKEU was operating Note This bit is set any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the Interrupt Mask Register or by resetting the PKEU 0 No internal error detected 1 Internal error 11 0 Reserved Write to zero for future compatibility CE 10 0 Context Error A PKEU key register the Key Size Register the Data Size...

Page 1298: ...0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field EVM INV IE CE KSE DSE ME AE Type R Reset 0x1000 Table 26 32 PKEUIMR Field Descriptions Name Reset Description Settings 63 15 0 Reserved Write to zero for future compatibility EVM 14 0 Even Modulus Error Enables disables interrupt generation 0 Even modulus error interrupt enabled 1 Even modulus error interrupt disabled INV 13 0 Inversion Error E...

Page 1299: ... four 2048 bit memories to receive and store operands for the arithmetic operations the PKEU will be asked to perform In addition results are stored in one particular parameter memory Data addressing within these memories is big endian that is the most significant byte is stored in the lowest address AE 6 0 Address Error Enables disables interrupt generation 0 Address error interrupt enabled 1 Add...

Page 1300: ... operates as one of the operands of the desired function as well as the result memory space For elliptic curve routines this memory is segmented in to four 512 bit memories and is used to specify particular curve parameters and input values as well as to store result values 26 5 6 10 3 PKEU Parameter Memory E This 2048 bit memory is non segmentable and stores the exponent for modular exponentiatio...

Page 1301: ...5 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field CE TS ED Type R W Reset 0x0000 Table 26 33 DEUMR Field Descriptions Name Reset Description Settings 63 3 0 Reserved Write to zero for futu...

Page 1302: ...crypt K3 to encrypt DEUKSR DEU Key Size Register Offset 0xC2008 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Key Size Type R W Reset 0x0000 Table 26 34 P...

Page 1303: ...ata size error Since all upper bits are ignored the entire message length in bits can be written to this register This register is cleared when the DEU is reset or reinitialized DEUDSR DEU Data Size Register Offset 0xC2010 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 2...

Page 1304: ...EU interrupts signalling done and error to reset It further resets the state of the DEU Interrupt Status Register 0 No reset 1 Reset interrupt logic MI 1 0 Module Initialization Setting this bit perform like a software reset except that the Interrupt Mask Register remains unchanged The module initialization includes execution of an initialization routine completion of which is indicated by the RD ...

Page 1305: ...ion Settings 63 24 0 Reserved Write to zero for future compatibility OFL 23 16 0 Output FIFO Length Indicates the number of 8 byte sets currently in the output FIFO IFL 15 8 0 Input FIFO Length Indicates the number of 8 byte sets currently in the input FIFO 7 6 0 Reserved Write to zero for future compatibility HALT 5 0 Halt Indicates whether the DEU is halted due to an error Note Because the error...

Page 1306: ...s a channel error interrupt to the controller DI 1 0 Done Interrupt This status bit reflects the state of the done interrupt signal as sampled by the controller Interrupt Status Register see Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 DEU is not signalling done 1 DEU is signalling done RD 0 0 Reset Done This status bit when high indicates that the DEU has completed i...

Page 1307: ...No internal error detected 1 Internal error ERE 11 0 Early Read Error Indicates whether the DEU IV register was read while the DEU was performing encryption 0 No early read error detected 1 Early read error CE 10 0 Context Error If set indicates that DEU key register the Key Size Register Data Size Register Mode Register or IV register was modified while DEU was performing encryption 0 No context ...

Page 1308: ...d FIFO size is not a limit to data input When operated through core processor controlled access the DEU cannot accept FIFO inputs larger than 256 bytes without overflowing 0 No input FIFO overflow error detected 1 Input FIFO overflow error OFU 1 0 Output FIFO Underflow If set the DEU output FIFO was read while empty 0 No output FIFO underflow error detected 1 Output FIFO underflow error OFO 0 0 Ou...

Page 1309: ...les interrupt generation 0 Interrupt enabled 1 Interrupt disabled DSE 8 0 Data Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled ME 7 0 Mode Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled AE 6 0 Address Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled OFE 5 0 Output FIFO Error Enables ...

Page 1310: ...data value is performed Reading from this register is not meaningful but a zero value is always returned and no error is generated Writing to this register is merely a trigger causing the DEU to process the final block of a message allowing it to signal done interrupt 26 5 7 9 DEU IV Register DEUIVR For CBC mode the initialization vector is written to and read from the DEU IV register The value of...

Page 1311: ...ad from anywhere in the DEU FIFO address space dequeues data from the DEU output FIFO Writes to the input FIFO go first to a staging register which can be written by byte 4 bytes or 8 bytes When all 8 bytes of the staging register have been written the entire 8 byte set is automatically enqueued into the FIFO If any byte is written twice between enqueues it causes an error interrupt of type AE fro...

Page 1312: ...22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field SCM ECM FN IM RDK CM ED Type R W Reset 0x0000 Table 26 40 AESUMR Field Descriptions Name Reset Description Settings 63 13 0 Reserved Write to zero for future compatibility SCM 12 0 Sub Cipher Mode Specifies the number of sources to be XORd together for specific cipher modes Note This field is included...

Page 1313: ... decrypted For details see Section 26 4 3 1 AESU Mode Register on page 26 41 0 Expand the user key prior to decrypting the first block 1 Do not expand the key The expanded decryption key is written after the context switch CM 2 1 0 Cipher Mode Used in combination with the ECM field to define the AES operating mode See Table 26 41 for details ED 0 0 Encryption Decryption Specifies whether to encryp...

Page 1314: ...is generated AESUKSR AESU Key Size Register Offset 0xC4008 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Key Size Type R W Reset 0x0000 Table 26 42 AESUKS...

Page 1315: ...nals the AESU to start processing data from the input FIFO as soon as it is available If the value of data size is modified during processing a context error is generated AESUDSR AESU Data Size Register Offset 0xC4010 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 ...

Page 1316: ...aling done and error to reset It further resets the state of the AESU Interrupt Status Register AESUISR 0 No reset 1 Reset interrupt logic MI 1 0 Module Initialization Setting this bit perform like a software reset except that the Interrupt Mask Register remains unchanged The module initialization includes execution of an initialization routine completion of which is indicated by the RD bit in the...

Page 1317: ...ptions Name Reset Description Settings 63 24 0 Reserved Write to zero for future compatibility OFL 23 16 1 Output FIFO Length The number of 8 byte sets currently in the output FIFO IFL 15 8 0 Input FIFO Length Indicates the number of 8 byte sets currently in the input FIFO 7 6 0 Reserved Write to zero for future compatibility HALT 5 0 Halt Indicates whether the RNG is halted due to an error Note B...

Page 1318: ...or interrupt signal as sampled by the controller Interrupt Status Register Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 AESU is not signaling error 1 AESU is signaling error DI 1 0 Done Interrupt This status bit reflects the state of the done interrupt signal as sampled by the controller Interrupt Status Register see Section 26 5 4 6 Controller Interrupt Status Regist...

Page 1319: ...RE 11 0 Early Read Error Indicates whether the AESU IV register was read while the AESU was processing 0 No early read error detected 1 Early read error CE 10 0 Context Error If set indicates that AESU key register the Key Size Register Data Size Register Mode Register or IV register was modified while the AESU was processing 0 No context error detected 1 Context error KSE 9 0 Key Size Error IF se...

Page 1320: ...and FIFO size is not a limit to data input When operated through core processor controlled access the AESU cannot accept FIFO inputs larger than 256 bytes without overflowing 0 No input FIFO overflow error detected 1 Input FIFO overflow error OFU 1 0 Output FIFO Underflow If set the AESU output FIFO was read while empty 0 No output FIFO underflow error detected 1 Output FIFO underflow error 0 0 Re...

Page 1321: ...interrupt generation 0 Interrupt enabled 1 Interrupt disabled KSE 9 0 Key Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled DSE 8 0 Data Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled ME 7 0 Mode Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled AE 6 0 Address Error Enables disable...

Page 1322: ...ext Registers are cleared when a hard or soft reset or initialization is performed The Context Registers must be read when changing context and restored to their original values to resume processing an interrupted message CBC CTR and CCM modes For CTR and CCM mode all seven 64 bit Context Registers must be read to retrieve context and all seven must be written back to restore context Effectively t...

Page 1323: ...d when changing context in decrypt mode To resume processing the value read must be written back to the key registers and the restore decrypt key bit must be set in the Mode Register This eliminates the overhead of expanding the key prior to starting decryption when switching context Note The AESU key registers are located at the following offsets AESUKR1 Offset 0xC4400 AESUKR2 Offset 0xC4408 AESU...

Page 1324: ...ny becomes available for reading If any byte is read twice between dequeues it causes an error interrupt of type AE from the EU Overflows and underflows caused by reading or writing the AESU FIFOs are reflected in the AESU Interrupt Status Register The AESU fetches data 128 bits at a time from the input FIFO During processing the input data is encrypted or decrypted with the key and initialization...

Page 1325: ...the Mode Register is modified during processing a context error is generated Table 26 48 describes MDEU Mode Register fields MDEUMR MDEU Mode Register Offset 0xC6000 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Rese...

Page 1326: ...et HMAC should be 0 0 Normal operation 1 Perform an SSL3 0 MAC operation INIT 4 0 Initialization Indicates whether to initialize the MDEU If initialization is not done the registers must be loaded from a hash context pointer in the descriptor When the data to be hashed is spread across multiple descriptors this bit must be 0 on all but the first descriptor 0 Do not initialize digest registers 1 Do...

Page 1327: ...ter Offset 0xC6008 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Key Size Type R W Reset 0x0000 MDEUDSR MDEU Data Size Register Offset 0xC6010 Bits 63 62 ...

Page 1328: ...et or reinitialized At the end of processing its contents are decremented down to zero unless there is an error interrupt Note Writing to the Data Size Register allows the MDEU to enter auto start mode Therefore always write the required Context Registers prior to writing the data size 26 5 9 4 MDEU Reset Control Register MDEURCR The MDEU Reset Control Register allows three levels reset for the MD...

Page 1329: ...lent to a hardware reset asserting the HRESET pin but the reset is restricted to the MDEU All registers and internal states are returned to the defined reset state 0 No reset 1 Full MDEU reset MDEUSR MDEU Status Register Offset 0xC6028 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R Reset 0x0000 Bits 3...

Page 1330: ...ge 26 84 0 MDEU is not signaling error 1 MDEU is signaling error DI 1 0 Done Interrupt This status bit reflects the state of the done interrupt signal as sampled by the controller Interrupt Status Register see Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 MDEU is not signalling done 1 MDEU is signalling done RD 0 0 Reset Done This status bit when high indicates that th...

Page 1331: ...14 0 Integrity Check Error If set indicates that an ICV check was performed and that the supplied ICV did not match the value computed by the MDEU 0 No error detected 1 Integrity check error 13 0 Reserved Write to zero for future compatibility IE 12 0 Internal Error Indicates whether the MDEU is locked and requires a reset before use Note This bit is set any time an enabled error condition occurs ...

Page 1332: ...Write to zero for future compatibility IFO 2 0 Input FIFO Overflow If set the MDEU input FIFO was pushed while full Note When operated through channel controlled access the SEC implements flow control and FIFO size is not a limit to data input When operated through core processor controlled access the MDEU cannot accept FIFO inputs larger than 256 bytes without overflowing 0 No input FIFO overflow...

Page 1333: ...t generation 0 Interrupt enabled 1 Interrupt disabled ERE 11 0 Early Read Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled CE 10 0 Context Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled KSE 9 0 Key Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled DSE 8 0 Data Size Error Enables disabl...

Page 1334: ... MDEU Mode Register on page 26 49 This register is cleared when the MDEU is reset or reinitialized MDEUICVSR MDEU ICV Size Register Offset 0xC6040 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14...

Page 1335: ...Registers MDEUCR For MDEU context consists of the hash plus the message length count Write access to this register block allows continuation of a previous hash Reading these registers provides the resulting message digest or HMAC along with an aggregate bit count Note SHA 1and SHA 256 are big endian MD5 is little endian The MDEU module internally reverses the endianness of the five registers A B C...

Page 1336: ...ia the MDEU Reset Control Register Section 26 5 9 4 MDEU Reset Control Register MDEURCR on page 26 140 or SEC global software reset Section 26 5 4 1 Master Control Register MCR on page 26 77 does not clear these registers 63 32 31 0 Context Offset Name A B 0xC_6100 MD 5 0x01234567 0x89ABCDEF SHA 1 0x67452301 0xEFCDAB89 SHA 224 0xC1059ED8 0x367CD507 SHA 256 0x6A09E667 0xBB67AE85 Name C D 0xC_6108 M...

Page 1337: ... in the MDEU FIFO address space enqueues data to the MDEU input FIFO and a read from anywhere in this address space returns all zeros When the core processor writes to the MDEU FIFO using core processor controlled access it can write to any FIFO address by byte 4 bytes or 8 bytes The MDEU assembles these bytes from left to right that is the first bytes written are placed in the most significant bi...

Page 1338: ... 0 Field CS DC PP Type R W Reset 0x0000 Table 26 53 AFEUMR Field Descriptions Name Reset Description Settings 63 3 0 Reserved Write to zero for future compatibility CS 2 0 Context Source If set causes the context to be moved from the input FIFO into the S box prior to starting encryption decryption Otherwise context should be directly written to the Context Registers or context should be generated...

Page 1339: ...ations specify keys of 5 16 bytes The device driver creates properly formatted descriptors for situations requiring a key permute prior to ciphering When using core processor controlled access typically for debug the user must perform the following sequence 1 Configure the AFEU Mode Register to perform a permute with key 2 Write the key data to AFEU key registers 3 Write the key size to the Key Si...

Page 1340: ... data must be written prior to writing the context data size The message data size must be written separately Note When reloading an existing context using core processor controlled access the user must write the context to the input FIFO then write the context size always 2072 bits The write of the context size indicates to the AFEU that all context is loaded The user then writes the message data...

Page 1341: ...0 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field RI MI SR Type R W Reset 0x0000 Table 26 54 AFEURCR Field Descriptions Name Reset Description Settings 63 3 0 Reserved Write to zero for future compatibility RI 2 0 Reset Interrupt Setting this bit causes AFEU interrupts signalling done and error to reset It further re...

Page 1342: ...d Descriptions Name Reset Description Settings 63 24 0 Reserved Write to zero for future compatibility OFL 23 16 0 Output FIFO Length The number of 8 byte sets currently in the output FIFO IFL 15 8 0 Input FIFO Length The number of 8 byte sets currently in the input FIFO 7 6 0 Reserved Write to zero for future compatibility HALT 5 0 Halt Indicates whether the AFEU is halted due to an error Note Be...

Page 1343: ...tus Registers CPSR 1 4 on page 26 92 and generates a channel error interrupt to the controller DI 1 0 Done Interrupt This status bit reflects the state of the done interrupt signal as sampled by the controller Interrupt Status Register Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 AFEU is not signaling done 1 AFEU is signaling done RD 0 0 Reset Done This status bit whe...

Page 1344: ...gister Data Size Register Mode Register or IV register was modified while the AESU was processing 0 No context error detected 1 Context error KSE 9 0 Key Size Error IF set indicates that a value outside the range 1 16 bytes written to the AFEU Key Size Register 0 No key size error detected 1 Key size error DSE 8 0 Data Size Error If set indicates that a value not a multiple of 8 bits was written t...

Page 1345: ...mit to data input When operated through core processor controlled access the AFEU cannot accept FIFO inputs larger than 256 bytes without overflowing 0 No input FIFO overflow error detected 1 Input FIFO overflow error OFU 1 0 Output FIFO Underflow If set the AFEU output FIFO was read while empty 0 No output FIFO underflow error detected 1 Output FIFO underflow error 0 0 Reserved Write to zero for ...

Page 1346: ... Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled DSE 8 0 Data Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled ME 7 0 Mode Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled AE 6 0 Address Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled OFE 5 0 Output...

Page 1347: ... Box memory consists of 256 bytes of SRAM each readable and writable as part of a 64 bit set The S Box contents should not be written with data unless that data was previously read from the S Box Context data should only be written if the AFEUMR PP bit is set see Section 26 5 10 1 AFEU Mode Register AFEUMR on page 26 150 After context data is written the context length must be written to the conte...

Page 1348: ...values to be used from the S Box Context must be loaded in the same order in which it was unloaded Note The AFEUCMPR is located at offset 0xC8200 26 5 10 11 AFEU Key Registers AFEUKR 1 2 AFEU uses two write only key registers to guide initial permutation of the AFEU S Box in conjunction with the AFEU Key Size Register AFEU performs permutation starting with the first byte of key register 0 and use...

Page 1349: ...eued from the FIFO so that the next 8 bytes if any becomes available for reading If any byte is read twice between dequeues it causes an error interrupt of type AE from the EU Overflows and underflow caused by reading or writing the AFEU FIFOs are reflected in the AFEUISR 26 5 11 KEU Registers 26 5 11 1 KEU Mode Register KEUMR The KEU Mode Register KEUMR contains several bits used to program the K...

Page 1350: ...is valid only when the ALG field is set to a function that uses F9 0 Normal operation no ICV comparison 1 After the ICV is computed compare it to the data in the KEU ICV_In register EDGE 5 0 Select EDGE A5 3 Blocks EDGE A5 3 requires that two 348 bit blocks be produced for every 4 615 mS slot If EDGE 1 the first five reads of the output FIFO retrieve the first 320 bits of block 1 The sixth read of...

Page 1351: ... multiple descriptors this bit should only be set in the descriptor that processes the first block of the message 0 Prevent Initialization 1 Enable Initialization 2 0 Reserved Write to zero for future compatibility ALG 1 0 0 Algorithm Selection Specifies the functions to perform 00 Perform F8 function only 01 reserved 10 Perform F9 function only 11 reserved KEUKSR KEU Key Size Register Offset 0xCE...

Page 1352: ...ost This register is cleared when the KEU is reset or reinitialized Writing to this register signals the KEU to start processing data from the input FIFO as soon as it is available If the value of data size is modified during processing a context error is generated KEUDSR KEU Data Size Register Offset 0xCE010 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type R W Reset 0x0000 Bits 47 ...

Page 1353: ...bility CLI 2 0 Clear Interrupts Setting this bit causes KEU interrupts signalling done and error to reset It further resets the KEU Interrupt Status Register KEUISR 0 Normal operation 1 Clear interrupts and KEUISR RI 1 0 Reinitialization Module initialization is almost the same as a software reset except that the Interrupt Mask Register remains unchanged Completion of the reinitialization is indic...

Page 1354: ... Reset Description Settings 63 24 0 Reserved Write to zero for future compatibility OFL 23 16 1 Output FIFO Length The number of 8 byte sets currently in the output FIFO IFL 15 8 1 Input FIFO Length The number of 8 byte sets currently in the input FIFO 7 6 0 Reserved Write to zero for future compatibility HALT 5 0 Halt Indicates whether the KEU is halted due to an error Note Because the error caus...

Page 1355: ...y the controller Interrupt Status Register Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 KEU is not signaling error 1 KEU is signaling error DI 1 0 Done Interrupt This status bit reflects the state of the done interrupt signal as sampled by the controller Interrupt Status Register Section 26 5 4 6 Controller Interrupt Status Register CISR on page 26 84 0 KEU is not sig...

Page 1356: ... enabled error condition occurs It can only be cleared by setting the corresponding bit in the KEUIMR or by resetting the KEU 0 No internal error detected 1 Internal error ERE 11 0 Early Read Error Indicates whether a KEU context or IV register was read while the KEU was processing 0 No early read error detected 1 Early read error CE 10 0 Context Error If set indicates that KEU key register the Ke...

Page 1357: ... FIFO error detected 1 Input FIFO non empty error 3 0 Reserved Write to zero for future compatibility IFO 2 0 Input FIFO Overflow If set the KEUU input FIFO was pushed while full 0 No input FIFO overflow error detected 1 Input FIFO overflow error OFU 1 0 Output FIFO Underflow If set the KEU output FIFO was read while empty 0 No output FIFO underflow error detected 1 Output FIFO underflow error 0 0...

Page 1358: ...terrupt generation 0 Interrupt enabled 1 Interrupt disabled KSE 9 0 Key Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled DSE 8 0 Data Size Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled ME 7 0 Mode Error Enables disables interrupt generation 0 Interrupt enabled 1 Interrupt disabled AE 6 0 Address Error Enables disables ...

Page 1359: ...KEUISR Note According to the ETSI SAGE 3GPP specification for F9 version 1 2 only 32 bits of the final MAC are used This is the lower 4 bytes of the KEUDOR KEUDOR KEU Data Out Register Offset 0xCE048 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field KEU Data Out F9 MAC Type R Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field KEU Data Out F9 MAC Type R Reset 0x0000 Bi...

Page 1360: ...essing the last block the value in the Data Size Register determines how many bits of the final message word 1 64 are processed The value written to this register has no significance A read of this register always returns a zero value KEUEOMR KEU End_of_ Message Register Offset 0xCE050 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38...

Page 1361: ...mmed correctly in accordance with the selected algorithm KEUIV1R KEU IV1 Register Offset 0xCE100 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field CE Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field CA CD CB Type R W Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field CC Type R W Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fi...

Page 1362: ...must be written to KEUICVIR before the data size is written KEUICVIR KEU ICV_In Register Offset 0xCE108 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field ICV_In Type R Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field ICV_In Type R Reset 0x0000 Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field ICV_In Type R Reset 0x0000 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 1363: ...ocessed with 3GPP F9 Once the initialization phase is completed KEUIV2R is not used during message processing KEUIV2R does not need to be written during context switches KEUIV2R KEU IV2 Register Offset 0xCE110 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field FRESH Type R W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Field FRESH Type R W Reset 0x0000 Bits 31 30 29 28...

Page 1364: ...eared when a hard soft reset or initialization is performed Note In typical operation a frame is received and processed in its entirety with the KEU performing session specific initialization using the contexts of KEU IV_1 and IV_2 registers The KEU Context Data and IV_1 registers should only be unloaded reloaded when the processing of a frame is discontinued prior to completion then processing is...

Page 1365: ...ocessing begins and cannot be written while the block is processing data or a context error will occur Reading from either of these registers results in an address error being reflected in the KEUISR KEUKDR1 KEU Key Data Registers 1 2 Offset 0xCE400 KEUKDR2 Offset 0xCE408 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field CK Type W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 3...

Page 1366: ...ess to these FIFOs For host controlled operation a write to anywhere in the KEU FIFO address space enqueues data to the KEU input FIFO and a read from anywhere in the KEU FIFO address space dequeues data from the KEU output FIFO Writes to the input FIFO go first to a staging register which can be written by byte 4 byte or 8 byte accesses When all 8 bytes of the staging register are written the ent...

Page 1367: ...nd the results are placed in the KEU Output FIFO During F9 processing the input data is hashed with the integrity key and the resulting MAC is placed in the KEU data out register The output size is the same as the input size Note The KEU input FIFO and output FIFO are located at offset 0xCE800 0CEFFF 26 5 12 RNG Registers 26 5 12 1 RNG Mode Register RNGMR The RNG Mode Register is a writable locati...

Page 1368: ...hout pushing data onto the FIFO Once the Data Size Register is written the RNG begins pushing data onto the FIFO Data is pushed onto the FIFO every 256 cycles until the FIFO is full The RNG then attempts to keep the FIFO full RNGDSR RNG Data Size Register Offset 0xCA010 Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Field Type W Reset 0x0000 Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ...

Page 1369: ... zero for future compatibility RI 2 0 Reset Interrupt Setting this bit causes RNG interrupts signalling done and error to reset It further resets the state of the RNG Interrupt Status Register 0 No reset 1 Reset interrupt logic MI 1 0 Module Initialization Setting this reinitializes the RNG to accept another request without forcing the internal control machines and the output FIFO to reset which w...

Page 1370: ...SR Field Descriptions Name Reset Description Settings 63 24 0 Reserved Write to zero for future compatibility OFL 23 16 1 Output FIFO Length The number of 8 byte sets currently in the output FIFO 15 6 0 Reserved Write to zero for future compatibility HALT 5 0 Halt Indicates whether the RNG is halted due to an error Note Because the error causing the RNG to stop operating may be masked before reach...

Page 1371: ...tatus Registers CPSR 1 4 on page 26 92 and generates a channel error interrupt to the controller If the Interrupt Status Register is written from the core processor 1s in the value written are recorded in the Interrupt Status Register if the corresponding bit is unmasked in the Interrupt Mask Register 1 0 Reserved Write to zero for future compatibility RD 0 0 Reset Done This status bit when high i...

Page 1372: ...umbers 0 No internal error detected 1 Internal error 11 8 0 Reserved Write to zero for future compatibility ME 7 0 Mode Error An illegal value was detected in the Mode Register 0 Valid data 1 Invalid data error AE 6 0 Address Error An illegal read or write address was detected within the RNG address space 0 No address error detected 1 Address error detected 5 2 0 Reserved Write to zero for future ...

Page 1373: ... compatibility IE 12 1 Internal Error An internal processing error was detected while generating random numbers 0 Internal error enabled 1 Internal error disabled 11 8 0 Reserved Write to zero for future compatibility ME 7 0 Mode Error An illegal value was detected in the Mode Register 0 Mode error enabled 1 Mode error disabled AE 6 0 Address Error An illegal read or write address was detected wit...

Page 1374: ...ll 8 bytes of the header are read that 8 bytes is automatically dequeued from the FIFO so that the next 8 bytes if any becomes available for reading If any byte is read twice between dequeues it causes an error interrupt of type AE from the EU Underflows caused by reading or writing the RNG output FIFO are reflected in the RNG Interrupt Status Register Also a write to the RNG output FIFO space wil...

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