MSC8144E Reference Manual, Rev. 3
26-162
Freescale
Semiconductor
Security Engine (SEC)
Register is modified during processing, a context error is generated. Table 26-58 describes the
KEU Mode Register bit fields.
Table 26-58. KEUMR Field Descriptions
Name
Reset
Description
Settings
—
63–8
0
Reserved. Write to zero for future compatibility.
GSM
7
0
Select GSM A5/3 Blocks
GSM A5/3 requires that two 114-bit blocks be
produced for every 4.615 mS slot. If GSM = 1, the
first read of the output FIFO retrieves the first
64-bits of block 1. The second read of the output
FIFO retrieves the next 50-bits of block 1 (the
remaining bits of this 64 bits are set to zero). The
third read of the output Fifo retrieves the first 64-bits
of block 2, and a fourth read of the output FIFO
retrieves the next 50-bits of block 2 (the remaining
bits of this 64 bits are set to zero).
If GSM = 0, 228 contiguous bits can be read with
successive reads of the output FIFO. In this case,
the host application is responsible for handling the
A5/3 block formatting.
Note:
If GSM = 1 and EDGE = 1, an error
interrupt is generated.
0
GSM A5/3 blocks not selected
1
GSM A5/3 blocks selected
CICV
6
0
Compare Integrity Check Values
If set, selects integrity check comparison. If the
ICVs do not match, an error interrupt is sent to the
channel. This field is valid only when the ALG field
is set to a function that uses F9.
0
Normal operation; no ICV comparison.
1
After the ICV is computed, compare it to the
data in the KEU ICV_In register.
EDGE
5
0
Select EDGE A5/3 Blocks
EDGE A5/3 requires that two 348-bit blocks be
produced for every 4.615 mS slot. If EDGE = 1, the
first five reads of the output FIFO retrieve the first
320-bits of block 1. The sixth read of the output
FIFO retrieves the final 28-bits of block 1 (the
remaining bits of the sixth 64-bit set are set to zero).
The next five reads of the output FIFO retrieve the
first 320-bits of block 2. The following read of the
output FIFO retrieves the final 28-bits of block 2 (the
remaining bits of this 64-bit set are set to zero).
If EDGE = 0, 696 contiguous bits can be read with
successive reads of the output FIFO. In this case
the host application is responsible for handling the
A5/3 block formatting.
Note:
If EDGE = 1 and GSM = 1, an error
interrupt is generated.
0
EDGE A5/3 blocks not selected
1
EDGE A5/3 blocks selected
PE
4
0
Process End_of_Message
Enables final processing of last message block fir
F9 only.
Note:
The PE bit should be set for F9 operations
if the 3G frame (or message) is processed
as a whole (not split across multiple
descriptors). If the frame is processed
across multiple descriptors, this bit should
only be set on the descriptor performing F9
processing on the final message block.
0
Prevent final block processing (message
incomplete)
1
Enable final block processing (message
complete)
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
