Execution Units
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
26-61
26.4.6.7 KEU Interrupt Mask Register
The KEU Interrupt Mask Register controls the result of detected errors. For a given error (as
defined in Section 26.5.11.6, KEU Interrupt Status Register (KEUISR), on page 26-167), if the
corresponding bit in this register is set, then the error is ignored; no error interrupt occurs and the
KEU Interrupt Status Register is not updated to reflect the error. If the corresponding bit is not
set, then upon detection of an error, the KEU Interrupt Status Register is updated to reflect the
error, causing assertion of the error interrupt signal, and causing the module to halt processing.
26.4.6.8 KEU Data Out Register (F9 MAC)
Following a done interrupt, the read-only KEU data out register holds the F9 message
authentication code. A 64-bit value is returned. This value may be truncated to 32 bits for some
applications. Writing to this location results in an address error being reflected in the KEU
Interrupt Status Register.
Note:
According to the ETSI/SAGE 3GPP specification for F9 (version 1.2), only 32 bits of
the final MAC are used. This is the lower 4 bytes of the KEU data out register.
26.4.6.9 KEU End_of_Message Register
The KEU End_of_Message Register signals the KEU that the final message block is written to
the input FIFO. Writing to this register causes the KEU to process the final block of a message,
allowing it to signal a done interrupt. When processing the last block, the value in the Data Size
Register determines how many bits of the final message set (1–64) are processed. The value
written to this register does not matter. A read of this register always returns a zero value.
26.4.6.10 KEU IV_1 Register
The KEU IV_1 register is a general purpose IV register used during the initialization phase of the
F8 algorithms for 3GPP, GSM A5/3, EDGE A5/3, GPRS GEA3 and also for the F9 algorithm for
3GPP. The user must write the appropriate value as defined by the standards for each algorithm
before a new message is started. Once the initialization phase is completed, the KEU IV_1
register is no longer used for the remainder of F8 or F9 processing. However, if 3GPP F9, is
selected, because the KEU IV_1 register contains the direction bit as defined by the 3GPP
standard, the KEU IV_1 register MUST be written back during context switches, to complete the
generation of the 3GPP MAC.
Note:
The user must ensure that fields of the IV_1 register are programmed correctly in
accordance with the selected algorithm.
26.4.6.11 KEU ICV_In Register
If ICV checking is required, then the value to compare with the computed F9 MAC value must be
written to the ICV_In register before data size is written.
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...