Global Interrupt Controller (GIC)
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
1-27
1.
The SC3400 core sets the registers in the controller with the message parameters (read
pointer, message length, destination, buffer size, available messages.)
— Optionally, the SC3400 core initiates only a pointer to a BD queue.
— The messaging controller reads the BD that includes the message parameters.
2.
The controller reads data from memory according to predefined parameters.
3.
The controller encapsulates the message and transfer it to a RapidIO endpoint.
4.
The RapidIO endpoint sends the message.
5.
Acknowledges are transferred from the RapidIO endpoint to the RMU.
6.
Upon completion of a message the controller can:
— Send an interrupt to the core, waiting for a new sets of parameters.
— Proceed to the next message in queue according to the previous parameters.
— Proceed to the next BD in queue.
The doorbell transmitter performs the following steps:
1.
The SC3400 core sets the registers in the controller with the doorbell parameters
(doorbell data, destination)
2.
The controller encapsulates the doorbell and transfers it to the RapidIO endpoint.
3.
The RapidIO endpoint sends the message.
4.
Acknowledges are transferred from the RapidIO endpoint to the RMU.
5.
Upon completion of a message the controller can send an interrupt to the SC3400 core
and wait for a new sets of parameters.
1.14
Global Interrupt Controller (GIC)
The GIC receives the external and internal
NMI
and maskable interrupt sources and routes them to
the SC3400 cores, to the
INT_OUT
lines, or to the
NMI_OUT
lines.
1.15
UART
The UART is used mainly for debugging. It provides a full-duplex port for serial
communications by transmit data (
TXD
) and receive data (
RXD
) lines. During reception, the
UART generates an interrupt request when a new character is available to the UART data
register. During transmission, the UART generates an interrupt request when its data register can
be written with new character. When accepting an interrupt request, an SC3400 core or external
host should read the UART status register to identify the interrupt source and service it
accordingly.
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...