JEDEC Standard DDR SDRAM Interface Commands
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
12-11
Refresh (similar to
MCAS
before
MRAS
). Causes a row to be read in all logical banks
(JEDEC SDRAM) as determined by the refresh row address counter. This refresh row
address counter is internal to the SDRAM. After it is read, the row is automatically
rewritten in the memory array. All logical banks must be in a precharged state before a
refresh. The memory controller also supports posted refreshes in which several refreshes
execute at once, and the refresh interval can be extended.
Mode register set (for configuration). Allows DDR SDRAM options to be set. These
options are:
MCAS
latency, additive latency (for DDR2), write recovery (for DDR2), burst
type, and burst length.
MCAS
latency may be chosen as provided by the preferred SDRAM
(some SDRAMs provide
MCAS
latency {1,2,3}, some provide
MCAS
latency {1,2,3,4},
and so on). Burst type is always sequential. Although some SDRAMs provide burst
lengths of 1, 2, 4, 8, and page size, this memory controller supports only a burst length of
4. The DDR memory controller executes the mode register set command during system
initialization. Parameters such as mode register data,
MCAS
latency, burst length, and burst
type, are set by software in DDR_SDRAM_MODE[SDMODE] and transferred to the
SDRAM array by the DDR memory controller after DDR_SDRAM_CFG[MEMEN] is
set. If DDR_SDRAM_CFG[BI] is set to bypass the automatic initialization, software can
configure the mode registers via the DDR_SDRAM_MD_CNTL register.
Self refresh. For use when the device is in standby for very long periods of time.
Automatically generates internal refresh cycles to keep the data in all memory banks
refreshed. Before execution of this command, the DDR controller places all logical bank
in a precharged state.
Table 12-7. DDR SDRAM Command Table
Operation
CKE
Previous
CKE
Current
MCS
MRAS
MCAS
MWE
MBA
MA10 MA
Activate
H
H
L
L
H
H
Logical bank select
Row
Row
Precharge select
logical bank
H
H
L
L
H
L
Logical bank select
L
X
Precharge all
logical banks
H
H
L
L
H
L
X
H
X
Read
H
H
L
H
L
H
Logical bank select
L
Column
Read with
auto-precharge
H
H
L
H
L
H
Logical bank select
H
Column
Write
H
H
L
H
L
L
Logical bank select
L
Column
Write with
auto-precharge
H
H
L
H
L
L
Logical bank select
H
Column
Mode register set
H
H
L
L
L
L
Opcode
Opcode
Opcode and
mode
Auto refresh
H
H
L
L
L
H
X
X
X
Self refresh
H
L
L
L
L
H
X
X
X
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
