Functional Description
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
15-11
operation and did not drive
PCI_DEVSEL
in the previous cycle, it delays the assertion of
PCI_DEVSEL
and
PCI_TRDY
for one cycle to allow the other target to get off the bus.
15.1.8.3.2 Dual Address Cycles
The VCOP supports dual address cycle (DAC) commands (64-bit addressing on PCI bus) as a
target only. DACs are different from single address cycles (SACs) in that the address phase takes
two PCI beats instead of one PCI beat to transfer (64-bit vs. 32-bit addressing). Only PCI
memory commands can use DAC cycles; I/O, configuration, interrupt acknowledge, and special
cycle command cannot use DAC cycles. The VCOP supports single-beat and burst DAC
transactions.
15.1.8.3.3 Data Streaming
The VCOP provides data streaming for PCI transactions to and from prefetchable memory. In
other words, when the VCOP is a target for a PCI initiated transaction, it supplies or accepts
multiple cache lines of data without disconnecting. For PCI transactions to non-prefetchable
space, the VCOP disconnects after the first data phase so that no streaming can occur.
For PCI memory reads, streaming is achieved by performing speculative reads from memory in
prefetchable space. A block of memory may be marked as prefetchable by setting the PCI
configuration registers bit for the inbound address translation (see page 15-42 for details) in the
following cases:
When reads do not alter the contents of memory (reads have no side effects)
When reads return all bytes regardless of the byte enable signals
When writes can be merged without causing errors
For a memory read command or a memory read line command, the VCOP reads one cache line
from memory. If the PCI read or read line transaction crosses a cache line boundary, the VCOP
starts the read of a new cache line. For a memory read multiple command, the VCOP reads two
cache lines from memory. When the PCI transaction finishes the read for the first cache line, the
VCOP performs a speculative read of a third cache line. The VCOP continues this prefetching
until the end of the transaction.
For PCI writes to memory, streaming is achieved by buffering the transaction in the space
available within the I/O sequencer. This allows PCI memory writes to execute with no wait
states.
A disconnect occurs if the VCOP runs out of buffer space on writes, or the VCOP cannot supply
consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also
occurs if the transaction crosses a 4K page boundary.
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
