Enhanced Time Processing Unit (eTPU2)
29-14
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Each channel input signal has an associated synchronizer made of two flip-flops sampling the signal on
every other eTPU clock, followed by a digital filter. This digital filter can work in three sub-modes, whose
purpose is to filter out noise pulses that have width less then a programmed value of eTPU clocks,
preventing these transitions from being input to the transition detect logic. The synchronizer and digital
filter are guaranteed to pass pulses that are greater than a programmed value. All channel input filters in
one Engine work on the same mode and sampling clock. For more information on channel input filters,
refer to
Section 29.3.4.4, Enhanced Digital Filter - EDF
. In one of the Angle Modes, the output of the
digital filter of channel 0 is replaced by the output of TCRCLK signal digital filter. Refer to the
eTPU
Reference Manual
for details.
29.2.2.3
Time Base Clock Signal — TCRCLK
TCRCLK is an input signal used to control the Time Bases TCR1 and TCR2. There is one independent
TCRCLK input for each Engine. For pulse accumulator operations TCRCLK can be used as a gate for a
counter based on the eTPU clock divided by eight. For Angle operations TCRCLK can be used to get the
tooth transition indications in Angle Mode.
Like the channel input signals, the TCRCLK signal has an associated synchronizer followed by a digital
filter. This digital filter can work in two sub-modes, whose purpose is to filter out noise pulses that have
width less then a programmed value of eTPU clocks, preventing these transitions from being input to the
transition detect logic. The synchronizer and digital filter are guaranteed to pass pulses that are greater than
a programmed value. The clock and operation sub-mode of the TCRCLK filter is configured
independently of the other channel input filters, through the field TCRCF in register ETPUTBCR. For
more information on filter sub-modes, refer to
Section 29.3.5.5, TCRCLK Digital Filter
Angle Modes, the output of the digital filter of channel 0 is replaced with the output of TCRCLK signal
digital filter.
29.2.2.4
eTPU Channel Output Disable Signals
Each eTPU engine has 4 input signals to force the outputs of a group of 8 channels to an inactive level.
When an input disable signal is active, all the channels in its group of 8 that have their ODIS bits set to 1
in ETPUCxCR register have their outputs forced to the opposite of the value specified in bit OPOL of the
same register. Therefore, channels can be individually selected to be affected by the output disable signals,
as well as their disabling forced polarity.
The output disable channel groups are defined in
Table 29-2. Output Disable Channel Groups
eMIOS Channel
Engine
Channels
11
A
0 to 7
10
8 to 15
9
16 to 23
8
24 to 31
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
