Flash Memory Array and Control
12-28
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
12.3
Functional Description
12.3.1
Flash
User Mode
In user mode the flash module can be read and written (register writes and interlock writes), programmed
or erased. The following sub-sections define all actions that can be performed in user mode.
12.3.2
Flash Read and Write
The default state of the flash module is read. The main and shadow address space can be read only in the
read state. The module configuration register (FLASH_x_MCR) is always available for read. The flash
module enters the read state on reset. The flash module is in the read state under these conditions:
•
The read state is active when PGM = 1 or ERS = 1 in the FLASH_x_MCR and high-voltage
operation is ongoing (read while write).
NOTE
Reads done to the partition(s) being operated on (either erased or
programmed) will result in an error and the RWE bit in the FLASH_x_MCR
will be set.
•
The read state is active when PGM = 1 and PSUS = 1 in the FLASH_x_MCR (program suspend).
•
The read state is active when ERS = 1 and ESUS = 1 and PGM = 0 in the FLASH_x_MCR (erase
suspend).
In flash user mode, registers can be written. Array can be written to do interlock writes.
Interlock writes attempted to invalid locations (due to blocks that do not exist in non 2
n
array sizes), will
result in an interlock occurring, but attempts to program or erase these blocks will not occur since they are
forced to be locked.
12.3.3
Read While Write (RWW)
The flash core is divided into partitions. Partitions are always comprised of two or more blocks. Partitions
are used to determine read-while-write (RWW) groupings. While a write (program or erase) is being done
within a given partition, a read can be simultaneously executed to any other partition. Partitions are listed
in
For each Flash array, the high address space of each RWW partition is physically comprised of two 256K
blocks as shown in
. However, because the high address space blocks are interleaved every 16
bytes between Flash array A and Flash array B, the practical size of the high address space RWW partitions
is effectively four 256K blocks.
The shadow block has unique RWW restrictions described in
Section 12.3.6, Flash Shadow Block
The FC is also divided into blocks to implement independent erase or program protection. The shadow
block exists outside the normal address space and is programmed, erased, and read independently of the
other blocks. The shadow block is included to support systems that require NVM for security or system
initialization information.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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