Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
13-8
Freescale Semiconductor
13.3.2.2
L1 Cache Control and Status Register 1 (L1CSR1)
The L1 Cache Control and Status Register 1 (L1CSR1) is a 32-bit register used for general control of the
instruction cache. The L1CSR1 register is accessed using a
mfspr
or
mtspr
instruction. The SPR number
for L1CSR0 is 1011 in decimal. The L1CSR1 register is shown below.
The L1CSR1 bits are described below.
30
DCINV
Data Cache Invalidate
0 No cache invalidate
1 Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once
complete, this bit is reset to ‘0’. Writing a ‘1’ while an invalidation operation is in
progress will result in an undefined operation. Writing a ‘0’ to this bit while an
invalidation operation is in progress will be ignored. Cache invalidation operations
require approximately 134 cycles to complete. Invalidation occurs regardless of the
enable (DCE) value.
During cache invalidations, the parity check bits are written with a value dependent on
the DCEDT selection. DCEDT should be written with the desired value for subsequent
cache operation when DCINV is set to ‘1’ for proper operation of the cache.
31
DCE
Data Cache Enable
0 Cache is disabled
1 Cache is enabled
When disabled, cache lookups are not performed for normal load or store accesses, or
for snoop requests.
Other L1CSR0 cache control operations are still available. Also, operation of the store
buffer is not affected by DCE.
1
These bits are not implemented and should be written with zero for future compatibility.
0
ICECE
ICEI
0
ICEDT
0
ICUL
ICLO
ICL
F
C
ICL
O
A
ICEA
0
ICABT
ICINV
ICE
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1011; Read/Write; Reset - 0x0
Figure 13-2. L1 Cache Control and Status Register 1 (L1CSR1)
Table 13-2. L1CSR1 Field Descriptions
Field
Description
0–14
Reserved
1
15
ICECE
Instruction Cache Error Checking Enable
0 Error Checking is disabled
1 Error Checking is enabled
Table 13-1. L1CSR0 Field Descriptions (continued)
Field
Description
Summary of Contents for PXR4030
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