Enhanced Time Processing Unit (eTPU2)
29-22
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29.2.5.2
ETPUCDCR - eTPU Coherent Dual-Parameter Controller Register
ETPUCDCR configures and controls dual-parameter coherent transfers. For more info, see
Section 29.3.4.2, Coherent Dual-parameter Controller - CDC
Figure 29-4. ETPUCDCR Register
STS — Start Bit
This bit is set by the host in order to start the data transfer between the parameter buffer pointed by
PBBASE and the target addresses selected by the concatenation of fields CTBASE and PARM0/1. The
host receives wait-states until the data transfer is complete, when this bit is reset by the coherency logic
(see
Section 29.3.4.2, Coherent Dual-parameter Controller - CDC
). Therefore, host always reads STS
as 0.
1 = (write) starts a coherent transfer.
0 = (write) does not start a coherent transfer.
CTBASE[0:4] — Channel Transfer Base
This field concatenates with fields PARM0/PARM1 to determine the absolute word offset (from the
SDM base) of the parameters to be transferred:
Parameter 0 word address = {CTBASE, PARM0} + SDM base word address
Parameter 1 word address = {CTBASE, PARM1} + SDM base word address
PBBASE[0:9] — Parameter Buffer Base Address
This field points to the base address of the parameter buffer location, with granularity of 2 parameters
(8 bytes). The host (byte) address of the first parameter in the buffer is PBBASE*8 + SDM Base Byte
Address. The microengine absolute (word) address of the first parameter in the buffer is PBBASE*2.
PWIDTH — Parameter Width Selection
This bit selects the width of the parameters to be transferred between the PB and the target address.
1 = Transfer 32-bit parameters. All 32 bits of the parameters are written in the destination address.
0 = Transfer 24-bit parameters. The upper byte remains unchanged in the destination address.
WR — Read/Write selection
Base + 0x004
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
STS
CTBASE
PBBASE
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PWID
TH
PARM0
WR
PARM1
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
