Peripheral Bridge (PBRIDGE)
15-6
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
15.3.1
Register Descriptions
There are three types of registers that control each PBRIDGE. All registers are 32-bit registers and must
be accessed in supervisor mode by trusted bus masters. Additionally, these registers must only be read
from or written to by a 32-bit aligned access. PBRIDGE registers are mapped into the PBRIDGE A and
PBRIDGE_B address spaces. The protection and access fields of the MPCR, PACR, and OPACR registers
are 4-bits wide. Although these registers are read/write, the reserved fields shown do not apply to this
device and must remain at the reset value, therefore only write the fields’ reset value to the reserved fields
of these registers.
15.3.1.1
Master Privilege Control Register (PBRIDGE_x_MPCR)
The master privilege control register (PBRIDGE_
x
_MPCR) specifies 4-bit access fields defining the
access privilege level associated with a bus master in the platform, as well as specifying whether write
accesses from this master are bufferable. The registers provide one field per bus master.
The following table describes the fields in the PBRIDGE master privilege control register:
Address: Base + 0x0000
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MBW0 MTR0 MTW0 MPL0 MBW1 MTR1 MTW1 MPL1
0
1
1
1
0
1
1
1
W
Reset
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MBW4 MTR4 MTW4 MPL4 MBW5 MTR5 MTW5 MPL5 MBW6 MTR6 MTW6 MPL6
0
1
1
1
W
Reset
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
Figure 15-2. Master Privilege Control Registers (PBRIDGE_x_MPCR)
Access Field 0
Access Field 1
Access Field 2
Access Field 3
Access Field 4
Access Field 5
Access Field 6
Access Field 7
Summary of Contents for PXR4030
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