Enhanced Queued Analog-to-Digital Converter (EQADC)
Freescale Semiconductor
27-7
PXR40 Microcontroller Reference Manual, Rev. 1
be sent to the RFIFOs until debug mode is exited. Commands whose execution has not started will not be
executed until debug mode is exited.The clock associated with an on-chip ADC stops, during its low phase,
after the ADC ceases executing commands. The time base counter will only stop after all on-chip ADCs
cease executing commands.
When exiting debug mode, the EQADC relies on the CFIFO operation modes and on the CFIFO status to
determine the next command entry to transfer.
The EQADC’s internal behavior after the debug mode entry request is detected differs depending on the
status of command transfers.
•
No command transfer is in progress.
The EQADC immediately halts future command transfers from any CFIFO.
•
Command transfer is in progress.
EQADC will complete the transfer and update CFIFO status before halting future command
transfers from any CFIFO. Command transfers to the internal CBuffers are considered completed
when a command is written to the buffers.
27.3.4
Stop Mode
Upon a stop mode entry request detection, the EQADC progressively halts its operations until it reaches a
static, stable state from which it can recover when returning to Normal mode. EQADC then asserts an
acknowledge signal, indicating that it is static and that the clock input can be stopped.The latter implies
that, as long as the platform clock is running, CFIFOs can still be triggered using software triggers, since
no scheme is implemented to write-protect registers during stop mode.
If at the time the stop mode entry request is detected, there are commands in the on-chip CBuffers that
were already under execution, these commands will be completed but the generated results, if any, will not
be sent to the RFIFOs until stop mode is exited. Commands whose execution has not started will not be
executed until stop mode is exited.
After these remaining commands are executed, the clock input to the ADCs and the bias generator circuit
is stopped. The ADC clock stops during its low phase. The time base counter will only stop after all
on-chip ADCs cease executing commands. Only then, the stop acknowledge signal is asserted. When
exiting stop mode, the EQADC relies on the CFIFO operation modes and on the CFIFO status to determine
the next command entry to transfer.
The EQADC internal behavior after the stop mode entry request is detected differs depending on the status
of the command transfer.
•
No command transfer is in progress
The EQADC immediately halts future command transfers from any CFIFO.
•
Command transfer is in progress
EQADC will complete the transfer and update CFIFO status before halting future command
transfers from any CFIFO. Command transfers to the internal CBuffers are considered completed
when a command is written to the buffers.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
