FlexRay Communication Controller (FLEXRAY)
Freescale Semiconductor
22-143
PXR40 Microcontroller Reference Manual, Rev. 1
•
(SSCCRn.VFR | SSCCRn.SYF | SSCCRn.NUF | SSCCRn.SUF) // count on frame condition
= 1;
and
•
((~SSCCRn.VFR |
vSS!ValidFrame
) & // valid frame restriction
(~SSCCRn.SYF |
vRF!Header!SyFIndicator
) & // sync frame indicator restriction
(~SSCCRn.NUF | ~
vRF!Header!NFIndicator
) & // null frame indicator restriction
(~SSCCRn.SUF |
vRF!Header!SuFIndicator
)) // startup frame indicator restriction
= 1;
NOTE
The indicator bits SYF, NUF, and SUF are valid only when a valid frame
was received. Thus it is required to set the VFR always, whenever count on
frame condition is used.
2. slot related condition:
•
((SSCCRn.STATUSMASK[3] &
vSS!ContentError
) | // increment on content error
(SSCCRn.STATUSMASK[2] &
vSS!SyntaxError
) | // increment on syntax error
(SSCCRn.STATUSMASK[1] &
vSS!BViolation
) | // increment on boundary violation
(SSCCRn.STATUSMASK[0] &
vSS!TxConflict
)) // increment on transmission conflict
= 1;
If the slot status counter is in single cycle mode, i.e. SSCCRn.MCY = 0, the internal slot status counter
SSCRn_INT is reset at each cycle start. If the slot status counter is in the multicycle mode, i.e.
SSCCRn.MCY = 1, the counter is not reset and incremented, until the maximum value is reached.
22.6.18.5 Message Buffer Slot Status Field
Each individual message buffer and each FIFO message buffer provides a slot status field, which provides
the information shown in
for the static/dynamic slot. The update conditions for the slot status
field depend on the message buffer type. Refer to the Message Buffer Update Sections in
Individual Message Buffer Functional Description
.
22.6.19 System Bus Access
This section provides a description of the system bus accesses performed by the controller.
All flexray memory data located in the system memory are accessed via the system bus. There are two
types of failures that can occur during the system bus access, the system bus illegal address access and the
system bus access timeout.
The behavior of the controller after the occurrence of a system bus failure is defined by the SBFF bit in
the
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
