Interrupts and Interrupt Controller (INTC)
Freescale Semiconductor
10-33
PXR40 Microcontroller Reference Manual, Rev. 1
One consequence of the priority comparator design is that once a higher priority interrupt request is
captured, it must be acknowledged by the CPU before a subsequent interrupt request of even higher
priority can be captured. For example, if the CPU is executing a priority level 1 interrupt, and a priority
level 2 interrupt request is captured by the INTC, followed shortly by a priority level 3 interrupt request,
the level 2 interrupt must be acknowledged by the CPU before a new level 3 interrupt will be generated.
10.4.2.2
LIFO
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are
stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt
exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and
stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software
vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.
The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 is not
preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14
entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and
popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities
first pushed are overwritten. A priority of 0 is an overwritten priority. However, the LIFO pop zeros if it
is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated
with the popping of an empty LIFO.
The LIFO is not memory mapped.
10.4.3
Details on Handshaking with Processor
10.4.3.1
Software Vector Mode Handshaking
10.4.3.1.1
Acknowledging Interrupt Request to Processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in
. The INTC
examines the peripheral and software configurable interrupt requests. When it finds an asserted peripheral
or software configurable interrupt request with a higher priority than PRI in INTC current priority register
(INTC_CPR), it asserts the interrupt request to the processor. The INTVEC field in INTC interrupt
acknowledge register (INTC_IACKR) is updated with the preempting interrupt request’s vector when the
interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the
interrupt request to the processor is asserted. The rest of the handshaking is described in
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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