Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-65
PXR40 Microcontroller Reference Manual, Rev. 1
a.
the Host CPU or CDC has done a data transfer during the last access arbitration slot for the
engine
. Also, the Host CPU does not hold a pending access against the other eTPU
microengine.
b.
the microengine is arbitrating for the access of its second parameter in a back-to-back access
All pairs of back-to-back parameter accesses are coherent with respect to Host and CDC (not
to the other microengine).
The direction (read or write) of any individual access by Host or microengine is irrelevant to the
arbitration. The use of Normal or PSE SDM area by the Host is also irrelevant to the arbitration.
The first parameter preloading in a TST is considered first access by the arbiter, regardless of any access
made at the END microinstruction of the previous thread, i.e.: the last access of a thread and the first
preload are never considered a back-to-back access. On the other hand, the TST preload accesses are
considered back-to-back and are, therefore, atomic with respect to Host or CDC.
NOTE
The Zero SDM operation (see the
eTPU Reference Manual
for details) is
considered an SDM access for arbitration purposes both on writes and reads;
the fact that read SDM data is discarded is irrelevant for arbitration.
29.3.4.4
Enhanced Digital Filter - EDF
The EDF eliminates passing of signal transitions which are caused by noise. Its purpose is to eliminate
false transition service requests caused by noise pulses which are shorter than a programmed width.
The EDF has three modes of operations, selected by the CDFC field in the ETPUECR register (see
Section 29.2.5.5, ETPUECR - eTPU Engine Configuration Register
). These modes offer selections of
trade-off between noise immunity and signal latency. CDFC also allows the filter to be bypassed.
gives an example of minimum detected signal pulse and maximum filtered noise pulse in the
three EDF operation modes. In Angle Mode, if AM=01, the EDF in channel 0 is replaced with the digital
filter and synchronizer of the TCRCLK signal. In this mode, channel 0 works in combination with the
Angle Counter logic, and their operation is fully synchronized.
Following subsections provide the functional description of the eTPU channel digital filter.
29.3.4.4.1
Two-Sample Mode
In this mode the EDF works like the TPU2/3 digital filter. It uses the filter clock which is the eTPU clock
divided by (2, 4, 8,.., 256) as a sampling clock. The filter clock is selected by the FPSCK field in the
ETPUECR - Engine Configuration Register (see
Section 29.2.5.5, ETPUECR - eTPU Engine
). The EDF compares two consecutive samples. If both samples have the same
value, the input signal state is updated. Note that when the FPSCK field selects the eTPU clock divided by
two, the EDF works like the TPU1 four-clock digital filter.
Summary of Contents for PXR4030
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