Memory Protection Unit (MPU)
16-16
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed by clearing
MPU_RGD
n
.Word3[VLD].
2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAAC
n
) would typically be performed.
Writes to the region descriptor using this alternate access control location do not affect the valid
bit, so there are, by definition, no coherency issues involved with the update. The access rights
associated with the memory region switch instantaneously to the new value as the peripheral write
completes.
3. If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGD
n
.Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses respectively and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.
4. Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
5. When the MPU detects an access error, the current AHB bus cycle is terminated with an error
response and information on the faulting reference captured in the MPU_EAR
n
and MPU_EDR
n
registers. The error-terminated AHB bus cycle typically initiates some type of error response in the
originating bus master. For example, a processor core may respond with a bus error exception,
while a data movement bus master may respond with an error interrupt. In any event, the processor
can retrieve the captured error address and detail information simply be reading the
MPU_E{A,D}R
n
registers. Information on which error registers contain captured fault data is
signaled by MPU_CESR[SPERR].
6. Finally, consider the use of overlapping region descriptors. Application of overlapping regions can
reduce the number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are logically summed
together (the boolean OR operator). In the following example of a dual-core system, there are four
bus masters: the two processors (CP0, CP1) and two DMA engines (eDMA, a traditional data
movement engine transferring data between RAM and peripherals, and FlexRAY, a second engine
transferring data to/from the RAM only). Consider the following region descriptor assignments:
Region Description
RGDn
CP0
CP1
eDMA
FlexRay
CP0 Code
0
rwx
r--
--
--
Flash
CP1 Code
1
r--
rwx
--
--
CP0 Data & Stack
2
rw-
---
--
--
RAM
CP0 -> CP1 Shared Data
3
r--
r--
--
--
CP1 -> CP0 Shared Data
CP0 Data & Stack
4
---
rw-
--
--
Shared DMA Data
5
rw-
rw-
rw
rw
Figure 16-10. Overlapping Region Descriptor Example
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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