Enhanced Time Processing Unit (eTPU2)
29-26
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
If eTPU Engine entered halt state, this flag is asserted. The flag remains asserted while the microengine
is in halt state, even during a single-step or forced instruction execution..
1 = eTPU Engine is halted
0 = eTPU Engine is not halted.
FCSS - Filter Clock Source Selection
Speeds up the filter clock source before the prescaler, allowing more input capture resolution at
minimum prescaling.
1 = use eTPU clock as EDF clock source before prescaler
0 = use eTPU clock / 2 as EDF clock source before prescaler.
NOTE
FCSS=1 also makes the channel work on T2/T4 timing mode (see
eTPU Reference Manual
).
FPSCK[0:2] — Filter Prescaler Clock Control
FPSCK controls the prescaling of the clocks used in digital filters for the channel input signals and
TCRCLK input, as shown in
. Filtering can be controlled independently by Engine, but all
input digital filters in the same Engine have same clock prescaling. For more details see
Section 29.3.4.4.5, Filter Clock Prescaler
.
A new value written to FPSCK only becomes effective when the filter prescaler finishes the current
count.
CDFC[0:1] — Channel Digital Filter Control
These bits select a digital filtering mode for the channels when configured as inputs for improved noise
immunity (refer to
). The eTPU has three digital filtering modes for the channels which
provide programmable trade-off between signal latency and noise immunity (see
). Changing CDFC during eTPU normal input channel operation is not
recommended since it changes the behavior of the transition detection logic while executing its
operation.
Table 29-6. Filter Prescaler Clock Control
Filter Control
Sample on
eTPU clock
Divided by:
000
2
001
4
010
8
011
16
100
32
101
64
110
128
111
256
Summary of Contents for PXR4030
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