Enhanced Modular Input/Output Subsystem (eMIOS200)
Freescale Semiconductor
23-63
PXR40 Microcontroller Reference Manual, Rev. 1
In order to ensure safe working and avoid glitches the following steps must be performed whenever any
update in the prescaling rate is desired:
1. Write 0 at both GPREN bit in EMIOSMCR register and UCPREN bit in EMIOS_CCR[
n
] register,
thus disabling prescalers;
2. Write the desired value for prescaling rate at UCPRE[] bits in EMIOS_CCR[
n
] register;
3. Enable channel prescaler by writing 1 at UCPREN bit in EMIOS_CCR[
n
] register;
4. Enable global prescaler by writing 1 at GPREN bit in EMIOSMCR register.
The prescaler is not disabled during either freeze state or negated GTBE input.
23.4.1.4
Effect of Freeze on the Unified Channel
When in debug mode, if the FRZ bit in the EMIOS_MCR register and the FREN bit in the
EMIOS_CCR[
n
] are both set, the internal counter and unified channel capture and compare functions are
halted. The unified channel is frozen in its current state.
During freeze, all registers are accessible. When the unified channel is operating in an output mode, the
force match functions remain available, allowing the software to force the output to the desired level.
During input modes, any input events that may occur while the channel is frozen are ignored.
When exiting debug mode or when the freeze enable bit is cleared (FRZ in the EMIOS_MCR or FREN in
the EMIOS_CCR[
n
] register), the channel actions resume but may be inconsistent until the channel enters
GPIO mode again.
23.4.2
IP Bus Interface Unit (BIU)
The BIU provides the interface between the internal interface bus (IIB) and the peripheral bus, allowing
communication among all submodules and this IP interface.
The BIU allows 8-, 16-, and 32-bit access. They are performed over a 32-bit data bus in a single cycle
clock.
23.4.2.1
Effect of Freeze on the BIU
When the FRZ bit in the EMIOS_MCR register is set and the module is in debug mode, the operation of
BIU is not affected.
23.4.3
STAC Client Submodule
The shared time and angle count (STAC) bus provides access to one external time base, imported from the
STAC bus to the eMIOS unified channels. The eTPU module's time bases and angle count can be exported
and/or imported through the STAC client submodule interface. Time bases and/or angle information of
either eTPU engine can be exported to the other eTPU engine and to the eMIOS module, which is only a
STAC client. There are restrictions on engine export/import targets: one engine cannot export from or
import to itself, nor can it import time base and/or angle count if in angle mode.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
