Enhanced Direct Memory Access Controller (eDMA)
Freescale Semiconductor
21-33
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 21-22. EDMA Hardware Request Status Register Low (EDMA_x_HRSL)
21.3.2.16 eDMA Global Write Registers (EDMA_x_GWRH and EDMA_x_GWRL)
The EDMA_x_GWRH and EDMA_x_GWRL registers provide coherency controls to the Cache
Coherency Unit (CCU). The EDMA_x_GWRH and EDMA_x_GWRL registers provide a bit map to
enable the CCU to snoop data writes from any enabled channel. When the Global Write Enable (GWEN)
bit for a channel is set, the eDMA will signal the CCU whenever that channel performs a write. The
EDMA_x_GWRH and EDMA_x_GWRL registers perform no functions within the eDMA.
21.3.2.17 eDMA Channel n Priority Registers (EDMA_x_CPRn)
When the fixed-priority channel arbitration mode is enabled (EDMA_
x
_MCR[ERCA] = 0), the contents
of these registers define the unique priorities associated with each channel. The channel priorities are
evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. If
software modifies channel priority values, then the software must ensure that the channel priorities contain
unique values. Otherwise, a configuration error is reported. The range of the priority value is limited to the
values of 0 through 15. When read, the GRPPRI bits of the EDMA_
x
_CPR
n
register reflect the current
priority level of the group of channels in which the corresponding channel resides. GRPPRI bits are not
affected by writes to the EDMA_
x
_CPR
n
registers. The group priority is assigned in the EDMA_
x
_MCR.
for the EDMA_
x
_MCR definition.
Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA
_x
_CPR
n
register. Channel preemption allows the executing channel’s data transfers to be temporarily suspended in
favor of starting a higher priority channel. After the preempting channel has completed all its minor loop
Address: EDMA_x_BASE + 0x0034
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R HRS
31
HRS
30
HRS
29
HRS
28
HRS
27
HRS
26
HRS
25
HRS
24
HRS
23
HRS
22
HRS
21
HRS
20
HRS
19
HRS
18
HRS
17
HRS
16
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R HRS
15
HRS
14
HRS
13
HRS
12
HRS
11
HRS
10
HRS
09
HRS
08
HRS
07
HRS
06
HRS
05
HRS
04
HRS
03
HRS
02
HRS
01
HRS
00
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 21-18. EDMA_x_HRSL Field Descriptions
Field
Description
0–31
HRSn
DMA Hardware Request Status
0 A hardware service request for channel n is not present.
1 A hardware service request for channel n is present.
Note: The hardware request status reflects the state of the request as seen by the arbitration logic.
Therefore, this status is affected by the EDMA_x_ERQRL[ERQn] bit.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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