Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-59
PXR40 Microcontroller Reference Manual, Rev. 1
29.3.3.2.2
Priority Passing Disabling
The priority passing scheme allows a case where a high priority channel looses to a lower priority one right
after another lower priority has been serviced, exemplified in the Cycle D on
. A middle
priority channel wins time slot 1 due to priority passing from high to middle. While it is being serviced,
two new service requests arrive, one high and one middle priority. The high priority request looses to the
middle one on next time slot 2 by default priority assignment.
This priority inversion can be avoided by setting the ETPUECR register bit SPPDIS (see
ETPUECR - eTPU Engine Configuration Register
), which disables the priority passing mechanism. When
priority passing is disabled, at the end of the thread the slot number is incremented until a time slot that
matches the priority of one of the requesting channel(s). The time slot advance takes no extra clocks. If no
channel requests service, the time slot counter stays at time slot 1. The priority selection scheme with
disabled priority passing is summarized in
.
An example of the priority passing disabling scheme is illustrated in
. The sequence of service
requests is the same as in the example of
, and although the time slot incrementing differs, the
priorities granted are the same for cycle B. Cycle C has one of the low priority channels serviced before
the second middle one. Cycle D, however, no longer has the priority inversion.
In cycle B, after the time slot 2 only a low priority request remains, so the time slot count advances directly
to 4, which has a low priority assigned. Time slot keeps on 4 for the next service, as only a low priority
request remains also, and only time slot 4 is assigned to low. Two high priority services contend for the
next time slot 5 (assigned to High). The second high priority channel is serviced on the next time slot,
jumped to 7 because there is no middle request, ending cycle B. Cycle C starts with time slot 2, as there
are no high priority requests and two middle and two low ones. After the first middle service, time slot
count skips 3 assigned to high (no high requests), and services a low priority channel on time slot 4. It
follows the same scheme until there are no other requests and cycle C is truncated, resetting the time slot
counter to 1.
Cycle D begins with a middle request, jumping to time slot 2. During this service two requests arrive, one
high and one middle. Unlike what happened with priority passing, the next serviced is the high priority
Table 29-18. Priority Passing Disabling
At the end
of time slot
servicin
g
priority
if any
request
of priority
service
it on time slot
else
if any
request
of priority
service
it on time slot
else
if any
request
of priority
service
it on time slot
1
High
Medium
2
High
3
Low
4
2
Medium
High
3
Low
4
Medium
6
3
High
Low
4
High
5
Medium
6
4
Low
High
5
Medium
6
Low
4
5
High
Medium
6
High
7
Low
4
6
Medium
High
7
Medium
2
Low
4
7
High
High
1
Medium
2
Low
4
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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