Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-27
PXR40 Microcontroller Reference Manual, Rev. 1
ERBA — Engine Relative Base Address
This field value is concatenated with the AID instruction field in engine relative address mode to form
the SDM address (see
eTPU Reference Manual
).
SPPDIS — Schedule Priority Passing Disable
SPPDIS is used to disable the priority passing mechanism of the microengine scheduler (see
Section 29.3.3.2.1, Primary Scheme - Priority Among Channels on Different Levels
).
1 = Scheduler priority passing mechanism disabled.
0 = Scheduler priority passing mechanism enabled.
NOTE
SPPDIS bit must not be changed while any channel is enabled.
ETB[0:4] — Entry Table Base
The field determines the location of the microcode entry table for the eTPU functions in SCM (see
eTPU Reference Manual
for details of how to use this field).
29.2.6
Time Base Registers
Time Base registers allows configuration and visibility of internally-generated time bases TCR1 and
TCR2. There is one of each of these registers for each eTPU Engine.
NOTE
Writes to this register issue bus error and are ineffective when MDIS=1.
Reads are always allowed.
Table 29-7. Channel Digital Filter Control
CDFC
Selected Digital Filter
00
TPU2/3 Two Sample Mode: Using the filter clock which is the eTPU clock divided by (2, 4,
8,.., 256) as a sampling clock (selected by FPSCK field in ETPUECR), comparing two
consecutive samples which agree with each other sets the input signal state. This is the
default reset state.
01
eTPU bypass mode: the input signal is taken unfiltered, also making the channels work on
T2/T4 timing mode
1
.
1
See eTPU Reference Manual
10
eTPU Three Sample Mode: Similar to the TPU2/3 two sample mode, but comparing three
consecutive samples which agree with each other sets the input signal state.
11
eTPU Continuous Mode: Signal need to be stable for the whole filter clock period. This
mode compares all the values at the rate of eTPU clock (FCSS=1) or eTPU clock divided
by two (FCSS=0), between two consecutive filter clock pulses. Signal needs to be
continuously stable for the entire period. If all the values agree with each other, input signal
state is updated.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
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