Enhanced Direct Memory Access Controller (eDMA)
21-34
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
data transfers, the preempted channel is restored and resumes execution. After the restored channel
completes one read/write sequence, it is again eligible for preemption. If any higher priority channel
requests service, the restored channel is suspended and the higher priority channel is serviced. Nested
preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel
begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected
for both group and channel arbitration modes.
A channel’s ability to pre-empt another channel can be disabled by setting EDMA
_x
_CPR[DPA]. When a
channel’s pre-empt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer;
regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data
moving channels to be defined. These low priority channels can be configured to not preempt each other,
thus preventing a low priority channel from consuming the preempt slot normally available a true, high
priority channel.
21.3.2.18 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
Address: EDMA_x_
BASE +
n
Access: User read/write
0
1
2
3
4
5
6
7
R
ECP
DPA
GRPPRI
CHPRI
W
Reset
0
0
0
0
1
The reset value for the channel priority field, CHPRI[0–3], is equal
to the corresponding channel number for each priority register;
that is, EDMA_x_CPRI0[CHPRI] = 0b0000 and
EDMA_x_CPR15[CHPRI] = 0b1111.
Figure 21-23. eDMA Channel n Priority Register (EDMA_x_CPRn)
Table 21-19. EDMA_x_CPRn Field Descriptions
Field
Description
0
ECP
Enable Channel Preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
1
DPA
Disable preempt ability.
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
2–3
GRPPRI
Channel n current group priority. Group priority assigned to this channel group when fixed-priority
arbitration is enabled. These two bits are read-only; writes are ignored. The reset value for the group
priority fields, is equal to the corresponding channel number for each priority register; that is,
EDMA_x_CPR31[GRPPRI] = 0b01.
4–7
CHPRI
Channel n Arbitration Priority. Channel priority when fixed-priority arbitration is enabled. The reset value
for the channel priority fields CHPRI[0–3], is equal to the corresponding channel number for each priority
register; that is, EDMA_x_CPR31[CHPRI] = 0b1111.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
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