Core (e200z7) Overview
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
13-35
13.9.10 Auxiliary Processor Unavailable Interrupt (IVOR9)
The PXR40 does not utilize this interrupt.
13.9.11 Decrementer Interrupt (IVOR10)
A Decrementer interrupt occurs when no higher priority exception exists, a Decrementer exception
condition exists (TSR
DIS
=1), and the interrupt is enabled (both TCR
DIE
and MSR
EE
=1).
The Timer Status Register (TSR) holds the Decrementer interrupt bit set by the Timer facility when an
exception is detected. Software must clear this bit in the interrupt handler to avoid repeated Decrementer
interrupts.
Table below lists register settings when a Decrementer interrupt is taken.
13.9.12 Fixed-Interval Timer Interrupt (IVOR11)
The triggering of the exception is caused by selected bits in the Time Base register changing from 0 to 1.
A Fixed-Interval Timer interrupt occurs when no higher priority exception exists, a FIT exception exists
(TSR
FIS
=1), and the interrupt is enabled (both TCR
FIE
and MSR
EE
=1).
The Timer Status Register (TSR) holds the FIT interrupt bit set by the Timer facility when an exception is
detected. Software must clear this bit in the interrupt handler to avoid repeated FIT interrupts.
DEAR
Unchanged
Vector
IVPR
0:15
|| IVOR8
16:27
|| 4b0000
Table 13-25. Decrementer Interrupt—Register Settings
Register
Setting Description
SRR0
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
SRR1
Set to the contents of the MSR at the time of the interrupt
MSR
UCLE 0
SPE
0
WE
0
CE
—
EE
0
PR
0
FP
0
ME
—
FE0
0
DE
—
FE1
0
IS
0
DS
0
PMM 0
RI
—
ESR
Unchanged
MCSR
Unchanged
DEAR
Unchanged
Vector
IVPR
0:15
|| IVOR10
16:27
|| 4b0000
Table 13-24. System Call Interrupt—Register Settings (continued)
Summary of Contents for PXR4030
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