Error Correction Status Module (ECSM)
Freescale Semiconductor
17-13
PXR40 Microcontroller Reference Manual, Rev. 1
17.2.2.13 RAM ECC Syndrome Register (ECSM_RESR)
The ECSM_RESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC
event in the RAM memory. Depending on the state of the ECC configuration register, an ECC event in the
RAM causes the address, attributes, and data associated with the access to be loaded into the
ECSM_REAR, ECSM_RESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the
appropriate flag (R1BC or RNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See
for the RAM
ECC syndrome register definition.
Offset:
ECSM_BAS 0x0060
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
REAR
W
Reset
U
1
1
U = undefined at reset
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
REAR
W
Reset
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Figure 17-10. RAM ECC Address (ECSM_REAR) Register
Table 17-11. ECSM_REAR Field Descriptions
Field
Description
0–31
REAR
RAM ECC Address Register. Contains the faulting access address of the last, properly-enabled RAM ECC event.
Offset: ECSM_BAS 0x0065
Access: User read-only
0
1
2
3
4
5
6
7
R
RESR[0:7]
W
Reset
U
1
1
U = undefined at reset
U
U
U
U
U
U
U
Figure 17-11. RAM ECC Syndrome (ECSM_RESR) Register
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
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