Peripheral Bridge (PBRIDGE)
Freescale Semiconductor
15-13
PXR40 Microcontroller Reference Manual, Rev. 1
15.4
Functional Description
The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as
a protocol translator. Support is provided for generating a pair of 32-bit peripheral accesses when targeted
by a 64-bit system bus instruction access. No other bus-sizing access support is provided.
Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module
selects for peripheral devices on the slave bus interface.
15.4.1
Access Support
Aligned 64-bit instruction accesses, aligned word and halfword accesses, as well as byte accesses are
supported for 32-bit peripherals. Do not misalign instruction accesses to peripheral registers, although no
explicit checking is performed by the PBRIDGE.
NOTE
Data accesses that cross a 32-bit boundary are not supported.
15.4.2
Peripheral Write Buffering
The PBRIDGE provides programmable write buffering capability to buffer write accesses in the
PBRIDGE for later completion, while terminating the system bus access early. This provides improved
performance in systems where frequent writes to a slow peripheral occur.
Write buffering is controllable on a per-master and per-peripheral basis. Enable write buffering for masters
and peripherals only when an error termination from the slave bus does not occur or is safe to ignore. When
write buffering is enabled, all accesses through the PBRIDGE must occur in sequence; bypassing buffered
writes is
not
supported.
NOTE
The core detects that the write buffering is complete before the write
actually completes in the peripheral. If write buffering is enabled for a
peripheral, the actual write takes an additional two system clock cycles plus
any additional system clock cycles the register requires. Most registers in
the MPC5500 family delay the write by two clock cycles, but some registers
take longer. This early termination, as detected by the core, can defeat the
mbar
or
msync
instruction between the write to clear a flag bit and the write
to the INTC_EOIR. Therefore, if write buffering is enabled for a peripheral
that has a flag bit, insert instructions between the
mbar
or
msync
instruction
and the write to the INTC_EOIR that consumes at least the number of
system clock cycles that the actual write is delayed.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
