Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
387
Operation
RS1 + RS2 + C
⇒
RD
Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary
addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the
previous operation allowing 32 and more bit additions.
Example:
ADD
R6,R2,R2
ADC
R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2
BCC
; conditional branch on 32 bit addition
CCR Effects
Code and CPU Cycles
ADC
Add with Carry
ADC
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000 and Z was set before this operation; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
new
| RS1[15] & RS2[15] & RD[15]
new
C:
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
new
| RS2[15] & RD[15]
new
Source Form
Address
Mode
Machine Code
Cycles
ADC RD, RS1, RS2
TRI
0
0
0
1
1
RD
RS1
RS2
1
1
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
