Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
548
Freescale Semiconductor
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents
are respectively the high and low byte of the PACB.
When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
14.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Module Base + 0x0025
7
6
5
4
3
2
1
0
R
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
W
Reset
0
0
0
0
0
0
0
0
Figure 14-40. Pulse Accumulators Count Register 0 (PACN0)
Module Base + 0x0026
7
6
5
4
3
2
1
0
R
MCZI
MODMC
RDMCL
0
0
MCEN
MCPR1
MCPR0
W
ICLAT
FLMC
Reset
0
0
0
0
0
0
0
0
Figure 14-41. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
