Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
424
Freescale Semiconductor
Operation
RS.H - IMM8 - C
⇒
NONE, only condition code flags get updated
Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of
the source register RD using binary subtraction and updates the condition code register accordingly. The
carry bit and Zero bits are taken into account to allow a 16 bit compare in the form of
CMPL
R2,#LOWBYTE
CPCH
R2,#HIGHBYTE
BCC
; branch condition
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
Code and CPU Cycles
CPCH
Compare Immediate 8 bit Constant with
Carry (High Byte)
CPCH
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $00 and Z was set before this operation; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & IMM8[7] & result[15] | RS[15] & IMM8[7] & result[15]
C:
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15]
Source Form
Address
Mode
Machine Code
Cycles
CPCH RD, #IMM8
IMM8
1
1
0
1
1
RS
IMM8
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
