Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
541
14.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1 (TSCR1)”
.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in
Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”
).
14.3.2.14 Timer Input Capture/Output Compare Registers 0–7
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
TOF
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-18. Main Timer Interrupt Flag 2 (TFLG2)
Table 14-17. TFLG2 Field Descriptions
Field
Description
7
TOF
Timer Overflow Flag
— Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
Module Base + 0x0010
15
14
13
12
11
10
9
8
R
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 14-19. Timer Input Capture/Output Compare Register 0 High (TC0)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
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indicated
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currently
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from
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for
import
or
sale
in
the
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prior
to
September
2010:
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products
in
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packages
