Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
402
Freescale Semiconductor
Operation
!(RS1[
w
:
0
] ^ RD[w+o:o])
⇒
RD[
w
+o:o];
w
= (RS2[7:4])
o
= (RS2[3:0])
Extracts
w+1
bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes
the bits back to RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored.
Using R0 as a RS1, this command can be used to toggle bits.
CCR Effects
Code and CPU Cycles
BFINSX
Bit Field Insert and XNOR
BFINSX
N
Z
V
C
∆
∆
0
—
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
V:
0; cleared.
C:
Not affected.
Source Form
Address
Mode
Machine Code
Cycles
BFINSX RD, RS1, RS2
TRI
0
1
1
1
1
RD
RS1
RS2
1
1
P
W4
O4
15
0
2
5
W4=3, O4=2
15
0
3
Bit Field Insert XNOR
RS2
RD
RS1
15
0
3
7
4
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
