Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
560
Freescale Semiconductor
If a 0x0000 is written into MCCNT when LATQ and BUFEN in ICSYS register are set, the input capture
and pulse accumulator registers will be latched.
With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag
in MCFLG register.
If the modulus down counter is enabled (MCEN = 1) and modulus mode is enabled (MODMC = 1), a write
to MCCNT will update the load register with the value written to it. The count register will not be updated
with the new value until the next counter underflow.
If modulus mode is not enabled (MODMC = 0), a write to MCCNT will clear the modulus prescaler and
will immediately update the counter register with the value written to it and down-counts to 0x0000 and
stops.
The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an
immediate load is desired.
14.3.2.32 Timer Input Capture Holding Registers 0–3 (TCxH)
Module Base + 0x0038
15
14
13
12
11
10
9
8
R
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-58. Timer Input Capture Holding Register 0 High (TC0H)
Module Base + 0x0039
7
6
5
4
3
2
1
0
R
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-59. Timer Input Capture Holding Register 0 Low (TC0H)
Module Base + 0x003A
15
14
13
12
11
10
9
8
R
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-60. Timer Input Capture Holding Register 1 High (TC1H)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
