Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
544
Freescale Semiconductor
Read: Anytime
Write anytime for output compare function. Writes to these registers have no meaning or effect during
input capture.
All bits reset to zero.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
14.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Read: Anytime
Write: Anytime
Module Base + 0x001D
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 14-32. Timer Input Capture/Output Compare Register 6 Low (TC6)
Module Base + 0x001E
15
14
13
12
11
10
9
8
R
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 14-33. Timer Input Capture/Output Compare Register 7 High (TC7)
Module Base + 0x001F
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 14-34. Timer Input Capture/Output Compare Register 7 Low (TC7)
Module Base + 0x0020
7
6
5
4
3
2
1
0
R
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-35. 16-Bit Pulse Accumulator Control Register (PACTL)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
