Random Number Generator (RNG)
Freescale Semiconductor
6-5
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
6.3
Functional Description
shows the RNG has three functional blocks: output FIFO, internal bus interface, and the RNG
core/control logic blocks. The following sections describe these blocks in more detail.
Figure 6-5. RNG Block Diagram
6.3.1
Output FIFO
RNGOUT stores the 32 bits of random data generated by the RNG core/control block. The RNGSR allows
the user to check if random data has been written to RNGOUT, through the output FIFO level field. If the
user reads from the FIFO when it is empty and the interrupt is enabled, the RNG drives an interrupt request
to the interrupt controller. It is very important to poll RNGSR[OFL] to make sure random values are
present before reading from RNGOUT.
6.3.2
RNG Core/Control Logic Block
This block contains the RNG’s control logic as well as its core engine that generates random data.
6.3.2.1
RNG Control Block
The control block contains the address decoder, all addressable registers, and control state machines for
the RNG. This block is responsible for communication with the peripheral interface and the FIFO
interface. The block also controls the core engine to generate random data. The general functionality of
the block is as follows. After reset, entropy generates and stores in the RNG’s shift registers. After
RNGCR[GO] is set, RNGOUT is loaded with a random word every 256 cycles.
6.3.2.2
RNG Core Engine
The core engine block contains the logic that generates random data. The logic within the core engine
contains the internal shift registers, as well as the logic that generates the two oscillator based clocks. This
logic is brainless and must be controlled by the control block. The control block controls how the shift
registers are configured and when the oscillator clocks are turned on.
RNG Core/Control
Output FIFO
Inter
n
al Bus
Logic
Internal Bus
Random Number
Generator
Internal
Control
Signals
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