Interrupt Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
15-8
NOTE
A spurious interrupt may occur if an interrupt source is being masked in the
interrupt controller mask register (IMR) or a module’s interrupt mask
register while the interrupt mask in the status register (SR[I]) is set to a value
lower than the interrupt’s level. This is because by the time the status
register acknowledges this interrupt, the interrupt has been masked. A
spurious interrupt is generated because the CPU cannot determine the
interrupt source.
To avoid this situation for interrupts sources with levels 1–6, first write a
higher level interrupt mask to the status register, before setting the mask in
the IMR or the module’s interrupt mask register. After the mask is set, return
the interrupt mask in the status register to its previous value. Because level
7 interrupts cannot be disabled in the status register prior to masking, use of
the IMR or module interrupt mask registers to disable level 7 interrupts is
not recommended.
15.3.3
Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCH
n
and INTFRCL
n
registers, each 32 bits, provide a mechanism to allow software generation
of interrupts for each possible source for functional or debug purposes. The system design may reserve one
or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force
request, 0 = negate request) in the appropriate INTFRC
n
register. The assertion of an interrupt request via
the INTFRC
n
register is not affected by the interrupt mask register. The INTFRC
n
register is cleared by
reset.
IPSBAR
Offset:
0x00_0C10 (INTFRCH0)
0x00_0D10 (INTFRCH1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
INTFRCH[63:32]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-5. Interrupt Force Register High (INTFRCHn)
Table 15-8. INTFRCHn Field Descriptions
Field
Description
31–0
INTFRCH
Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
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part
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import
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sale
in
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
