Clock Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
7-5
7.6.2
XTAL
This output is an internal oscillator connection to the external crystal.
7.6.3
CLKOUT
This output reflects the internal system clock.
7.6.4
RSTO
The RSTO pin is asserted by one of the following:
•
Internal system reset signal
•
FRCRSTOUT bit in the reset control status register (RCR); see
Section 10.5.1, “Reset Control
7.7
Memory Map and Registers
The clock module programming model shown in
consists of registers that define clock operation
and status as well as additional peripheral power management registers.
7.7.1
Register Descriptions
This subsection provides a description of the clock module registers.
Table 7-3. Clock Module Memory Map
IPSBAR
Offset
1
1
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Register
Width
(bits)
Access
Reset Value
Section/Page
Supervisor Mode Access Only
0x0012_0000
Synthesizer Control Register (SYNCR)
16
R/W
0x1002
0x0012_0002
Synthesizer Status Register (SYNSR)
8
R
0x00
0x0012_0007
Low Power Control Register (LPCR)
8
R/W
0x00
0x0012_0008
Clock Control High Register (CCHR)
8
R/W
0x04
0x0012_000C Real Time Clock Divide Register (RTCDR)
32
R/W
0x00000000
0x0000_000C Peripheral Power Management Register High (PPMRH)
2
2
See
Section 9.2.1, “Peripheral Power Management Registers (PPMRH, PPMRL).”
32
R/W
0x00000000
0x0000_0008
Peripheral Power Management Register Low (PPMRL)
32
R/W
0x00000001
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
