Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-50
Freescale Semiconductor
NOTE
When the software driver sets an E bit in one or more receive descriptors,
the driver should follow that with a write to RDAR.
18.6.3
Ethernet Transmit Buffer Descriptor (TxBD)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.
The Ethernet controller confirms transmission by clearing the ready bit (R bit) when DMA of the buffer is
complete. In the TxBD the user initializes the R, W, L, and TC bits and the length (in bytes) in the first
longword, and the buffer pointer in the second longword.
The FEC sets the R bit equal to 0 in the first longword of the BD when the buffer has been DMA’d. Status
bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is
indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See
Section 18.5.3, “MIB Block Counters Memory Map
” for more details.
0
Bit 5
LG
Rx frame length violation. Written by the FEC. A frame length greater
than RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is
set. The receive data is not altered in any way unless the length exceeds
2047 bytes.
0
Bit 4
NO
Receive non-octet aligned frame. Written by the FEC. A frame that
contained a number of bits not divisible by 8 was received, and the CRC
check that occurred at the preceding byte boundary generated an error.
This bit is valid only if the L-bit is set. If this bit is set, the CR bit is not set.
0
Bit 3
—
Reserved.
0
Bit 2
CR
Receive CRC error. Written by the FEC. This frame contains a CRC error
and is an integral number of octets in length. This bit is valid only if the
L-bit is set.
0
Bit 1
OV
Overrun. Written by the FEC. A receive FIFO overrun occurred during
frame reception. If this bit is set, the other status bits, M, LG, NO, CR,
and CL lose their normal meaning and is zero. This bit is valid only if the
L-bit is set.
0
Bit 0
TR
Set if the receive frame is truncated (frame length > 2047 bytes). If the
TR bit is set the frame should be discarded and the other error bits
should be ignored as they may be incorrect.
2
Bits [15:0]
Data Length
Data length. Written by the FEC. Data length is the number of octets
written by the FEC into this BD’s data buffer if L equals 0 (the value is
equal to EMRBR) or the length of the frame, including CRC if L equals 1.
It is written by the FEC once as the BD is closed.
4
Bits [15:0]
A[31:16]
RX data buffer pointer, bits [31:16]
1
6
Bits [15:0]
A[15:0]
RX data buffer pointer, bits [15:0]
1
The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 16. The
buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
Table 18-36. Receive Buffer Descriptor Field Definitions (continued)
Word
Location
Field Name
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
