Interrupt Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
15-12
controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also
cleared.
15.3.8
Global Level m IACK Registers (GLmIACK)
In addition to the software IACK registers (
Section 15.3.7, “Software and Level m IACK Registers
), there are global IACK registers, GL
m
IACK. (There is no global SWIACK
register.) On devices with multiple interrupt controllers, a read from one of the GL
m
IACK registers returns
the vector for the highest priority unmasked interrupt within a level for all interrupt controllers.
IPSBAR
Offsets:
for register offsets
(SWIACKn, LmIACKn)
Access: read-only
7
6
5
4
3
2
1
0
R
VECTOR
W
Reset:
0
0
0
0
0
0
0
0
Figure 15-10. Software and Level m IACK Registers (SWIACKn, LmIACKn)
Table 15-14. SWIACKn and LmIACKn Field Descriptions
Field
Description
7–0
VECTOR
Vector number. A read from the SWIACK register returns the vector number associated with the highest level,
highest priority unmasked interrupt source. A read from one of the LmIACK registers returns the highest priority
unmasked interrupt source within the level.
IPSBAR
Offsets:
for register offsets
(GLmIACK)
Access: read-only
7
6
5
4
3
2
1
0
R
VECTOR
W
Reset:
0
0
0
0
0
0
0
0
Figure 15-11. Global Level m IACK Registers (GLmIACK)
Table 15-15. GSWIACK and GLmIACK Field Descriptions
Field
Description
7–0
VECTOR
Vector number. A read from one of the LmIACK registers returns the vector for the highest priority unmasked
interrupt within a level for all interrupt controllers.
As implemented on the MCF52, these registers contain the same information as LmIACK.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
