Freescale Semiconductor
24-1
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 24
DMA Timers (DTIM0–DTIM3)
24.1
Introduction
This chapter describes the configuration and operation of the four direct memory access (DMA) timer
modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference
compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally,
programming examples are included.
NOTE
The designation
n
appears throughout this section to refer to registers or
signals associated with one of the four identical timer modules: DTIM0,
DTIM1, DTIM2, or DTIM3.
24.1.1
Overview
Each DMA timer module has a separate register set for configuration and control. The timers can be
configured to operate from the internal bus clock (fsys) or from an external clocking source using the
DTIN
n
signal. If the internal bus clock is selected, it can be divided by 16 or 1. The selected clock source
is routed to an 8-bit programmable prescaler that clocks the actual DMA timer counter register (DTCN
n
).
Using the DTMR
n
, DTXMR
n
, DTCR
n
, and DTRR
n
registers, the DMA timer may be configured to assert
an output signal, generate an interrupt, or request a DMA transfer on a particular event.
NOTE
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to
Chapter 14, “General Purpose I/O Module”
)
prior to configuring the DMA Timers.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
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available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
