Interrupt Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
15-17
Freescale Semiconductor
15.4
Low-Power Wakeup Operation
The system control module (SCM) contains an 8-bit low-power interrupt control register (LPICR) used
explicitly for controlling the low-power stop mode. This register must explicitly be programmed by
software to enter low-power mode.
The interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to
exit from the low-power stop mode. This special mode of operation works as follows:
1. LPICR[6:4] is loaded with the specified mask level while the core is in stop mode. LPICR[7] must
be set to enable this mode of operation.
NOTE
The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to
allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value
used by the interrupt controller must be in the range of 0–6.
2. The processor executes a STOP instruction which places it in stop mode. After the processor is
stopped, each interrupt controller enables a special logic path that evaluates the incoming interrupt
sources in a purely combinatorial path; that is, there are no clocked storage elements. If an active
interrupt request is asserted and the resulting interrupt level is greater than the mask value
contained in LPICR[6:4], then the interrupt controller asserts the wake-up output signal, which is
routed to the SCM and PLL module to re-enable the device’s clock trees and resume processing.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
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available
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for
import
or
sale
in
the
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
